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Z8F082ASH020SC Datasheet(PDF) 112 Page - Zilog, Inc. |
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Z8F082ASH020SC Datasheet(HTML) 112 Page - Zilog, Inc. |
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112 / 244 page  PS024705-0405 P R E L I M I N A R Y UART Z8 Encore! XP® F08xA Seriess Product Specification 94 Figure 14.UART Receiver Interrupt Service Routine Flow Baud Rate Generator Interrupts If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt asserts when the UART Baud Rate Generator reloads. This condition allows the Baud Rate Generator to function as an additional counter if the UART functionality is not employed. UART Baud Rate Generator The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans- mission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value Receiver Errors? No Yes Read Status Discard Data Read Data which Interrupt Receiver Ready clears RDA bit and resets error bits Read Data |
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