AD9161BBCZ datasheet(111/144 Pages) AD

111 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 111 of 144

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

0x311 SYNC_GEN_0

[7:3] RESERVED

Reserved.

0x0

EOMF_MASK_0

Mask EOMF from QBD_0. Assert

SYNCOUT based on loss of

multiframe sync.

0x0

R/W

0 Don not assert SYNCOUT on

loss of multiframe.

1 Assert SYNCOUT on loss of

multiframe.

RESERVED

Reserved.

0x0

R/W

EOF_MASK_0

Mask EOF from QBD_0. Assert

SYNCOUT based on loss of

frame sync.

0x0

R/W

0 Do not assert SYNCOUT on loss

of frame.

1 Assert SYNCOUT on loss of

frame.

0x312 SYNC_GEN_1

[7:4] SYNC_ERR_DUR

Duration of SYNCOUT signal

low for purpose of sync error

report. 0 means half PCLK cycle.

Add an additional PCLK = 4

octets for each increment of the

value.

0x0

R/W

[3:0] SYNC_SYNCREQ_DUR

Duration of SYNCOUT signal

low for purpose of sync request.

0 means 5 frame + 9 octets. Add

an additional PCLK = 4 octets

for each increment of the value.

0x0

R/W

0x313 SYNC_GEN_3

[7:0] LMFC_PERIOD

LMFC period in PCLK cycle. This

is to report the global LMFC

period based on PCLK.

0x0

0x315 PHY_PRBS_TEST_EN

[7:0] PHY_TEST_EN

Enable PHY BER by ungating

the clocks.

0x0

R/W

1 PHY test enable.

0 PHY test disable.

0x316 PHY_PRBS_TEST_CTRL

RESERVED

Reserved.

0x0

[6:4] PHY_SRC_ERR_CNT

0x0

R/W

000 Report Lane 0 error count.

001 Report Lane 1 error count.

010 Report Lane 2 error count.

011 Report Lane 3 error count.

100 Report Lane 4 error count.

101 Report Lane 5 error count.

110 Report Lane 6 error count.

111 Report Lane 7 error count.

[3:2] PHY_PRBS_PAT_SEL

Select PRBS pattern for PHY BER

test.

0x0

R/W

00 PRBS7.

01 PRBS15.

10 PRBS31.

11 Not used.

PHY_TEST_START

Start and stop the PHY PRBS

test.

0x0

R/W

0 Test not started.

1 Test started.

PHY_TEST_RESET

Reset PHY PRBS test state

machine and error counters.

0x0

R/W

0 Not reset.

1 Reset.

AD9161BBCZ Datasheet(PDF) 111 Page - Analog Devices

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