AD9161BBCZ datasheet(115/144 Pages) AD

115 / 144 page

Data Sheet

AD9161/AD9162

Rev. D | Page 115 of 144

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

0x405 K_REG

[7:5] RESERVED

Reserved.

0x0

[4:0] K_RD

Received ILAS configuration on

Lane 0. K is the number of

frames per multiframe. Settings

of 16 or 32 are valid. On this

device, all modes use K = 32

(value in register is K − 1). Link

information received on Lane 0

as specified in Section 8.3 of

JESD204B.

0x0

01111 16 frames per multiframe.

11111 32 frames per multiframe.

0x406 M_REG

[7:0] M_RD

Received ILAS configuration on

Lane 0. M is the number of

converters per device. Link

information received on Lane 0

as specified in Section 8.3 of

JESD204B. M is 1 for real

interface and 2 for complex

interface (value in register is M

− 1).

0x0

0x407 CS_N_REG

[7:6] CS_RD

Received ILAS configuration on

Lane 0. CS is the number of

control bits per sample. Link

information received on Lane 0

as specified in Section 8.3 of

JESD204B. CS is always 0 on this

device.

0x0

RESERVED

Reserved.

0x0

[4:0] N_RD

Received ILAS configuration on

Lane 0. N is the converter

resolution. Value in register is N

− 1 (for example, 16 bits =

0b01111).

0x0

0x408 NP_REG

[7:5] SUBCLASSV_RD

Received ILAS configuration on

Lane 0. SUBCLASSV is the

device subclass version. Link

information received on Lane 0

as specified in Section 8.3 of

JESD204B.

0x0

000 Subclass 0.

001 Subclass 1.

[4:0] NP_RD

Received ILAS configuration on

Lane 0. NP is the total number

of bits per sample. Link

information received on Lane 0

as specified in Section 8.3 of

JESD204B. Value in register is

NP − 1, for example, 16 bits per

sample = 0b01111.

0x0

0x409 S_REG

[7:5] JESDV_RD

Received ILAS configuration on

Lane 0. JESDV is the JESD204x

version. Link information

received on Lane 0 as specified

in Section 8.3 of JESD204B.

0x0

000 JESD204A.

001 JESD204B.

[4:0] S_RD

Received ILAS configuration on

Lane 0. S is the number of

samples per converter per

frame cycle. Link information

received on Lane 0 as specified

in Section 8.3 of JESD204B.

Value in register is S − 1.

0x0

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