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AD9161BBCZ Datasheet(PDF) 119 Page - Analog Devices |
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AD9161BBCZ Datasheet(HTML) 119 Page - Analog Devices |
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119 / 144 page ![]() Data Sheet AD9161/AD9162 Rev. D | Page 119 of 144 Hex. Addr. Name Bits Bit Name Settings Description Reset Access [4:0] L Number of lanes per converter (minus 1). L is the number of lanes per converter device. Settings of 1, 2, 3, 4, 6, and 8 are valid. Refer to Table 16 and Table 17. 0x7 R 0x454 ILS_F [7:0] F Number of octets per frame (minus 1). This value of F is not used to soft configure the QBD. Register CTRLREG1 is used to soft-configure the QBD. 0x0 R 0x455 ILS_K [7:5] RESERVED Reserved. 0x0 R [4:0] K Number of frames per multiframe (minus 1). K is the number of frames per multiframe. On this device, all modes use K = 32 (value in register is K − 1). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x1F R/W 01111 16 frames per multiframe. 11111 32 frames per multiframe. 0x456 ILS_M [7:0] M Number of converters per device (minus 1). M is the number of converters/device. Settings of 1 and 2 are valid. Refer to Table 16 and Table 17. 0x1 R 0x457 ILS_CS_N [7:6] CS Number of control bits per sample. CS is the number of control bits per sample. Must be set to 0. Control bits are not supported. 0x0 R 5 RESERVED Reserved. 0x0 R [4:0] N Converter resolution (minus 1). N is the converter resolution. Must be set to 16 (0x0F). 0xF R 0x458 ILS_NP [7:5] SUBCLASSV Device subclass version. SUBCLASSV is the device subclass version. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x0 R/W 000 Subclass 0. 001 Subclass 1. 010 Subclass 2 (not supported.) [4:0] NP Total number of bits per sample (minus 1) NP is the total number of bits per sample. Must be set to 16 (0x0F). Refer to Table 16 and Table 17. 0xF R 0x459 ILS_S [7:5] JESDV JESD204x version. JESDV is the JESD204x version. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. 0x0 R/W 000 JESD204A. 001 JESD204B. |
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