AD9161BBCZ datasheet(118/144 Pages) AD

118 / 144 page

AD9161/AD9162

Data Sheet

Rev. D | Page 118 of 144

Hex.

Addr. Name

Bits Bit Name

Settings

Description

Reset

Access

0x450 ILS_DID

[7:0] DID

Device (= link) identification

number. DID is the device ID

number. Link information

received on Lane 0 as specified

in Section 8.3 of JESD204B.

Must be set to the value read in

only be programmed while the

QBD is held in soft reset

(Register 0x475, Bit 3), and must

not be changed during normal

operation.

0x0

R/W

0x451 ILS_BID

[7:0] BID

Bank ID, extension to DID. This

signal must only be

programmed while the QBD is

held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x0

R/W

0x452 ILS_LID0

RESERVED

Reserved.

0x0

ADJDIR

Direction to adjust DAC LMFC

(Subclass 2 only). ADJDIR is the

direction to adjust DAC LMFC.

Link information received on

Lane 0 as specified in Section

8.3 of JESD204B. This signal

must only be programmed

while the QBD is held in soft

reset (Register 0x475, Bit 3), and

must not be changed during

normal operation.

0x0

R/W

PHADJ

Phase adjustment to DAC

(Subclass 2 only). PHADJ is the

phase adjustment request to

the DAC. Link information

received on Lane 0 as specified

in Section 8.3 of JESD204B. This

signal must only be

programmed while the QBD is

held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x0

R/W

[4:0] LID0

Lane identification number

(within link). LID0 is the lane

identification for Lane 0. Link

information received on Lane 0

as specified in Section 8.3 of

JESD204B. This signal must only

be programmed while the QBD

is held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x0

R/W

0x453 ILS_SCR_L

SCR

Scramble enable. SCR is the Rx

descrambling enable. This

signal must only be

programmed while the QBD is

held in soft reset (Register

0x475, Bit 3), and must not be

changed during normal

operation.

0x1

R/W

0 Descrambling is disabled.

1 Descrambling is enabled.

[6:5] RESERVED

Reserved.

0x0

AD9161BBCZ Datasheet(PDF) 118 Page - Analog Devices

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