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AD9161BBCZ Datasheet(PDF) 116 Page - Analog Devices

Part # AD9161BBCZ
Description  11-Bit/16-Bit, 12 GSPS, RF Digital-to-Analog Converters
PDF  144 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9161BBCZ Datasheet(HTML) 116 Page - Analog Devices

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AD9161/AD9162
Data Sheet
Rev. D | Page 116 of 144
Hex.
Addr. Name
Bits Bit Name
Settings
Description
Reset
Access
0x40A HD_CF_REG
7
HD_RD
Received ILAS configuration on
Lane 0. HD is the high density
format. Refer to Section 5.1.3 of
JESD204B standard. Link
information received on Lane 0
as specified in Section 8.3 of
JESD204B.
0x0
R
0 Low density mode.
1 High density mode.
[6:5] RESERVED
Reserved.
0x0
R
[4:0] CF_RD
Received ILAS configuration on
Lane 0. CF is the number of
control words per frame clock
period per link. Link information
received on Lane 0 as specified
in Section 8.3 of JESD204B. CF is
always 0 on this device.
0x0
R
0x40B RES1_REG
[7:0] RES1_RD
Received ILAS configuration on
Lane 0. Reserved Field 1. Link
information received on Lane 0
as specified in Section 8.3 of
JESD204B.
0x0
R
0x40C RES2_REG
[7:0] RES2_RD
Received ILAS configuration on
Lane 0. Reserved Field 2. Link
information received on Lane 0
as specified in Section 8.3 of
JESD204B.
0x0
R
0x40D CHECKSUM0_REG
[7:0] LL_FCHK0
Received checksum during ILAS
on Lane 0. Checksum for Lane 0.
Link information received on
Lane 0 as specified in Section
8.3 of JESD204B.
0x0
R
0x40E COMPSUM0_REG
[7:0] LL_FCMP0
Computed checksum on Lane 0.
Computed checksum for Lane
0. The JESD204B Rx computes
the checksum of the link
information received on Lane 0
as specified in Section 8.3 of
JESD204B. The computation
method is set by the
CHECKSUM_MODE bit
(Register 0x300, Bit 6) and must
match the likewise calculated
checksum in Register 0x40D.
0x0
R
0x412 LID1_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID1
Received ILAS LID configuration
on Lane 1. Lane identification
for Lane 1. Link information
received on Lane 0 as specified
in Section 8.3 of JESD204B.
0x0
R
0x415 CHECKSUM1_REG
[7:0] LL_FCHK1
Received checksum during ILAS
on lane 1. Checksum for Lane 1.
Link information received on
Lane 0 as specified in Section
8.3 of JESD204B.
0x0
R
0x416 COMPSUM1_REG
[7:0] LL_FCMP1
Computed checksum on Lane 1.
Computed checksum for Lane 1
(see description for Register
0x40E).
0x0
R
0x41A LID2_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID2
Received ILAS LID configuration
on Lane 2. Lane identification
for Lane 2.
0x0
R
0x41D CHECKSUM2_REG
[7:0] LL_FCHK2
Received checksum during ILAS
on Lane 2. Checksum for Lane 2.
0x0
R



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