ADPD4200 datasheet(40/93 Pages) AD

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Data Sheet

ADPD4200

APPLICATIONS INFORMATION

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Rev. 0 | 40 of 93

Sleep Float Mode

The recommended operating mode for an ECG measurement with

the ADPD4200 is sleep float mode. In sleep float mode, a robust

ECG measurement can be made regardless of whether low impe-

dance wet electrodes or high impedance dry electrodes are used.

Sleep float mode is also suitable for ECG measurements with large

half cell potential mismatches.

In sleep float mode, the capacitor floats during other time slots

and during sleep, accumulating charge from the ECG signal. The

accumulated charge is then transferred into the integrator during

a specified time slot. The device must be configured to float the

inputs during the preconditioning period and during sleep. The

inputs are connected to the external capacitor only during the

charge transfer time. At all other times, the inputs are floating,

resulting in a float time of 1/tP, where tP is the sampling rate of the

ADPD4200. For example, if the ADPD4200 is set up to sample at

300 Hz, the float time in sleep float mode is ~3.3 ms.

An advantage of using sleep float mode is reduced power con-

sumption. While the sampling capacitor is floating, it is disconnect-

ed from the amplifier, and there is no need for the amplifier power

to be on. Using sleep float mode can reduce power consumption

by using the sleep time, when the amplifiers are powered down, to

transfer the ECG signal from the body to the sampling capacitor. A

timing diagram for sleep float mode is shown in Figure 39.

The relevant register settings for sleep float mode are shown in

Table 24.

Figure 39. Sleep Float Mode Timing Diagram

Table 24. Relevant Configuration Registers for ECG Measurement Using Sleep Float Mode

Group

Time Slot A

Bit Field Name

Description

Signal Path Setup

0x0100, Bits[13:12]

SAMPLE_TYPE_x

Leave at the default setting (0) for default sampling mode.

0x0100, Bits[11:10]

INPUT_R_SELECT_x

Set to 0x0 for 500 Ω series input resistor.

0x0101, Bits[8:0]

AFE_PATH_CFG_x

Set to 0x0E6 for TIA, integrator, and ADC. Bypass the BPF.

0x0101, Bits[15:12]

PRE_WIDTH_x

Set to 0 to skip preconditioning period.

0x0102, Bits[15:12],

0x0102, Bits[3:0]

INPxx_x

Set to 0x7 to enable desired inputs connected to Channel 1 as defined in PAIRxx.

0x0103, Bits[14:12]

PRECON_x

Set to 0x0 to float the inputs during preconditioning.

0x0020, Bits[15:12],

0x0020, Bits[3:0]

INP_SLEEP_xx

Set to 0x0 to float inputs during sleep.

0x0021, Bit 3, 0x0021, Bit

PAIRxx

Set to 1 to configure selected inputs as a differential pair.

0x0104, Bits[5:0]

TIA_GAIN_CHx_x

Select TIA gain.

0x0104, Bits[9:8]

AFE_TRIM_VREF_x

Set to 0x2 to set TIA_VREF = 0.9 V.

Float Mode

Configuration

0x0107, Bits[15:8]

NUM_INT_x

Set to 1 for a single integration per group of ADC conversions.

0x0107, Bits[7:0]

NUM_REPEAT_x

Number of sequence repeats.

0x0108, Bits[13:12]

MOD_TYPE_x

Set to 0x1 for float type operation.

0x0108, Bits[9:0]

MIN_PERIOD_x

Set to 0. Minimum period is not applicable to sleep float mode with a single integration.

0x010A, Bits[4:0]

INTEG_WIDTH_x

Integration time in µs. Set to MOD_WIDTH_x + 1.

0x010A, Bits[14:12],

0x010A, Bits[10:8]

CHx_AMP_DISABLE_x

Set 0x010A, Bit 9 to 1 to power down the BPF for Channel 1, and Bit 13 to 1 to power

down the BPF for Channel 2 if Channel 2 is enabled.

0x010B, Bits[12:0]

INTEG_OFFSET_x

Integration sequence start time. Set to (MOD_OFFSET_x − INTEG_WIDTH_x – 250 ns).

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