ADPD4200 datasheet(28/93 Pages) AD

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Data Sheet

ADPD4200

APPLICATIONS INFORMATION

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Setting the ZERO_ADJUST_x bit = 1, which adds 2048 codes to

the end result.

Figure 26. Diagram of Integrator Chopping Sequence

Table 17. Register Settings for Integrator Chop Mode

Group

Time Slot A Register Address1

Bit Field Name

Description

Integrator Chop Mode

0x010D, Bits[7:4]

SUBTRACT_x

Four-pulse subtract pattern. Set to 1 to

negate the math operation in the matching

position in a group of four pulses. The LSB

maps to the first pulse.

0x010D, Bits[3:0]

REVERSE_INTEG_x

Four-pulse integration reverse pattern. Set

to 1 to reverse the integrator positive

and negative pulse order in the matching

position in a group of four pulses. The LSB

maps to the first pulse.

1 This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x010D is the location for

SUBTRACT_A. For Time Slot B, this register is at Address 0x012D. For Time Slot C, this register is at Address 0x014D. For Time Slot D, this register is at Address 0x016D,

and so on.

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