XM014035B datasheet(97/101 Pages) XMOS

97 / 101 page

XU6--FB6 Datasheet

Schematics Design Check List

This section is a checklist for use by schematics designers using the XU6-

-FB6. Each of the following sections contains items to check for

each design.

Power supplies

The VDD (core) supply is capable of supplying ,

mA (Section

and

Figure

PLL_AVDD is ltered with a low pass lter, for example an RC lter, see Sec-

tion

PLL_AVDD is ltered with a low pass lter, for example an RC lter, see

Section

If any of the VDDIOL, VDDIOT, or VDDIOR domains are at V8, then then

the corresponding LV_L_N, LV_T_N, or LV_R_N pin has been strapped to

GROUND (Section ).

Power supply decoupling

The design has multiple decoupling capacitors per supply, as specied in

Section .

A bulk decoupling capacitor of at least uF is placed on each supply (Sec-

tion ).

Power on reset

At least one of these two conditions is true:

. All VDDIO pins are supplied by the same .8V supply (the on-chip power-

on-reset will operate correctly); or

. RST_N is kept low until all VDDIO are valid, and RST_N is fast enough to

meet USB timings.

See Section .

Clock

If you put a crystal between XIN/XOUT you followed the guidelines in Sec-

tion . .

If you supply a clock directly onto XIN, then it is .8V, low jitter, and has

monotonic edges.

XM014035B Datasheet(PDF) 97 Page - Xmos Ltd.