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XM014035B Datasheet(PDF) 18 Page - Xmos Ltd.

Part # XM014035B
Description  XCore - Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 265-FBGA (14x14)
PDF  101 Pages
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Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.

XM014035B Datasheet(HTML) 18 Page - Xmos Ltd.

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XU6--FB6 Datasheet
Core PLL
Secondary PLL
xCORE0 divider
Switch divider
xCORE1 divider
REF clk divider
Oscillator
output divider
output divider
700 MHz
24 MHz
700
MHz
700
MHz
700
MHz
X1D11
clock blocks
100 MHz
÷2
Fractional
N divider
control
xCORE1
Switch
xCORE0
XIN
XOUT
PSWITCH_PLL_CLK_DIVIDER
SSWITCH_SWITCH_CLK_DIVIDER
PSWITCH_PLL_CLK_DIVIDER
SSWITCH_REF_CLK_DIVIDER
SSWITCH_PLL_CTL
SSWITCH_SS_APP_PLL_CTL
SSWITCH_SS_APP_PLL
_FRAC_N_DIVIDER
PS_XCORE_CTRL0
PS_XCORE_CTRL0
App clock divider
SSWITCH_SS_APP_CLK_DIVIDER
Core 1
port 1D
out
in
Watchdog
MIPI cfg divider
÷2
MIPI demux divider
÷2
200
MHz
100
MHz
MIPI Rx PHY
MIPI demux
SSWITCH_MIPI_CLK_DIVIDER
SSWITCH_MIPI_CGF_CLK_DIVIDER
USB PHY
LPDDR divider
÷2
100
MHz
LPDDR
Controller
X0D58
X0D57
SWITCH_DDR_CLK_DIVIDER
Core 0
port 32A
out[9]
out[8]
Figure :
Clock
structure
Oscillator
Tile Boot
PLL Ratio
PLL settings
Frequency
Frequency
OD
F
R
8-
MHz
-
MHz
6.66
Figure 8:
The initial PLL
multiplier
values
Figure 8 lists the oscillator frequency range, and the values of OD, F and R, which are
the registers that dene the ratio of the tile frequency to the oscillator frequency:
Fcore = Fosc ×
F + 1
2
×
1
R + 1
×
1
OD + 1
OD
, F and R must be chosen so that 0 ≤ R ≤ 63, 1 ≤ F ≤ 8191, 0 ≤ OD ≤ 7, and
360
MHz ≤ Fosc × F+1
2
×
1
R+1 ≤ 1800MHz. The OD, F , and R values can be modied
by writing to the digital node PLL conguration register, see Appendix D. .
If a different tile frequency is required (eg,
MHz), then the PLL must be reprogrammed
after boot to provide the required tile frequency. The XMOS tools perform this operation
by default.
.
Secondary PLL
The secondary PLL can be used for generating clocks inside the device, or to create an
application clock
out of the device. When used as an application clock, the output is
routed to pin to pin XD and port D on core as is shown in Figure . The clock output
is divided down to between
Hz and
MHz. When enabled, tile can input the clock



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