XM014035B datasheet(5/101 Pages) XMOS

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XU6--FB6 Datasheet

XU6--FB6 Features

Multicore Microcontroller with Advanced Multi-Core RISC Architecture

• 6 real-time logical cores on xCORE tiles

• Cores share up to

MIPS

— Up to

MIPS in dual issue mode

— Up to

MFLOPS

• Each logical core has:

— Guaranteed throughput of between / and /8 of tile MIPS

— 6xbit dedicated registers

•

high-density 6/-bit instructions

— All have single clock-cycle execution (except for divide)

—

x →6-bit MAC instructions for DSP, arithmetic and cryptographic functions

• Vector unit, capable of:

— up to eight word, 6 half-word, or

byte multiply-adds.

— quad complex multiply, or

6 bit-wide multiply-adds.

USB PHY, fully compliant with USB . specication

MIPI receiver, up to two lanes, up to . Gbit/s

Application PLL with fractional control

Programmable I/O

•

8 general-purpose I/O pins, congurable as input or output

— Up to

x bit port,

x bit port, 8 x 8bit port, x 6bit port, x

bit port

— 8 xCONNECT links

• Port sampling rates of up to 6 MHz with respect to an external clock

• 6 channel ends (

per tile) for communication with other cores, on or off-chip

• .8V/.V IO with programmable drive strength

Memory

• MB internal single-cycle SRAM (KB per tile) for code and data storage

• 8KB internal OTP (shared between tiles or split providing KB per tile) for application boot code

Hardware resources

•

clock blocks (6 per tile)

•

timers ( per tile)

• 8 locks ( per tile)

JTAG Module for On-Chip Debug

Security Features

• Programming lock disables debug and prevents read-back of memory contents

• AES bootloader ensures secrecy of IP held on external ash memory

Ambient Temperature Range

• °C to

°C

Speed Grade

•

: 6

MHz; up to

MIPS,

MFLOP/s, 8. GMACC/s

•

: 8

MHz; up to

MIPS, 6

MFLOP/s, . GMACC/s

Power Consumption

•

mA (typical)

6-pin FBGA package .8 mm pitch

XM014035B Datasheet(PDF) 5 Page - Xmos Ltd.

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