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XM014035B Datasheet(PDF) 49 Page - Xmos Ltd.

Part # XM014035B
Description  XCore - Microcontroller IC 32-Bit 16-Core 2400MIPs 8KB (8K x 8) OTP 265-FBGA (14x14)
PDF  101 Pages
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Manufacturer  XMOS [Xmos Ltd.]
Direct Link  https://www.xmos.ai/
Logo XMOS - Xmos Ltd.

XM014035B Datasheet(HTML) 49 Page - Xmos Ltd.

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XU6--FB6 Datasheet
B.
xCORE Tile boot status
BOOT_CONFIG 0x03
This read-only register describes the boot status of the xCORE tile.
Bits
Perm
Init
Description
Identier
:
RO
-
Reserved
:6
RO
Processor number.
BOOT_CONFIG_PROCESSOR
:
RO
-
Reserved
8
RO
Overwrite BOOT_MODE.
BOOT_CONFIG_SECURE_BOOT
:
RO
-
Reserved
RO
Cause the ROM to not poll the OTP for correct read levels
BOOT_CONFIG_DISABLE_OTP_POLL
RO
Boot ROM boots from RAM
BOOT_CONFIG_BOOT_FROM_RAM
RO
Boot ROM boots from JTAG
BOOT_CONFIG_BOOT_FROM_JTAG
:
RO
The boot PLL mode pin value.
BOOT_CONFIG_PLL_MODE_PINS
x:
xCORE Tile
boot status
B.
Security conguration
SECURITY_CONFIG 0x05
Copy of the security register as read from OTP.
Bits
Perm
Init
Description
Identier
RW
Disables write permission on this register
SECUR_CFG_DISABLE_ACCESS
:
RO
-
Reserved
RW
Disable access to XCore’s global debug
SECUR_CFG_DISABLE_GLOBAL_DEBUG
:
RO
-
Reserved
RW
Disable read access to OTP.
SECUR_CFG_OTP_READ_LOCK
8
RW
Prevent access to OTP SBPI interface to prevent programming and
other functions.
SECUR_CFG_OTP_PROGRAM_DISABLE
RW
Combine OTP into a single address-space for reading.
SECUR_CFG_OTP_COMBINED
6
RO
-
Reserved
RW
Override boot mode and read boot image from OTP SECUR_CFG_SECURE_BOOT
RW
Disable JTAG access to the PLL/BOOT conguration registers
SECUR_CFG_DISABLE_PLL_JTAG
:
RO
-
Reserved
RW
Disable access to XCore’s JTAG debug TAP
SECUR_CFG_DISABLE_XCORE_JTAG
x:
Security
conguration
8



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