XM014035B datasheet(31/101 Pages) XMOS

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XU6--FB6 Datasheet

the xCORE Tile based on this pin. This pin should have an external pull up of K-K Ω

or left not connected in single core applications.

The JTAG device identication register can be read by using the IDCODE instruction. Its

contents are specied in Figure .

Bit

Device Identication Register

Bit

Version

Part Number

Manufacturer Identity

Figure

IDCODE return

value

The JTAG usercode register can be read by using the USERCODE instruction. Its con-

tents are specied in Figure 8. The OTP User ID eld is read from bits [:] of the

OTP_JTAG_USER_WORD on xCORE Tile , see Section . (all zero on unprogrammed

devices). The OTP User ID eld is set by the boot ROM when it executes after the device

reset has been de-asserted, so its value is not available to read when the device is in

reset.

Bit

Usercode Register

Bit

OTP User ID

Silicon Revision

Figure 8:

USERCODE

return value

You can program the PLL and reset the device over JTAG. When IR is set to eight, the DR

value is shifted directly into the PLL settings register (Appendix D. ), which includes bits

for resetting the device and for setting the “boot-from-JTAG” bit. Note that if TCK is not

free running then at least

TCK clocks must be provided after shifting the value into

DR for the write to take effect.

Board Integration

The device has power and ground pins for different supplies. Several pins of each type

may be provided to minimize the effect of inductance within the package, all of which

must be connected.

VDD pins for the xCORE Tile. The VDD supply should be well decoupled at high frequen-

cies. Place many (at least )

nF low inductance multi-layer ceramic capacitors

close to the chip between the supplies and GND.

VDDIO pins for the I/O lines. Separate I/O supplies are provided for the left, bottom, top,

and right side of the package; different I/O voltages may be supplied on those. The sig-

nal description (Section ) species which I/O is powered from which power-supply.

The VDDIO supplies should be decoupled close to the chip by several

nF low in-

ductance multi-layer ceramic capacitors between the supplies and GND, for example,

one

low inductance MLCCs on each supply pin. If you use .8V for any

of the VDDIOL, VDDIOT, or VDDIOR domains, then you must strap the corresponding

LV_L_N, LV_T_N, or LV_R_N pins to GROUND

PLL_AVDD pin for the PLL, with an associated PLL_AGND. The PLL_AVDD supply should

be separated from the other noisier supplies on the board. The PLL requires a very

clean power supply, and a low pass lter (for example, a µF multi-layer ceramic

XM014035B Datasheet(PDF) 31 Page - Xmos Ltd.

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