XM014035B datasheet(29/101 Pages) XMOS

29 / 101 page

XU6--FB6 Datasheet

PORT_1J

PORT_1I

PORT_8B

CLKBLK

RXD

PORT_1H

CLKBLK

PORT_1K

PORT_8A

TXD

xCORE

USB

connector

ID connection is optional

DM may be marked as DN

USB_VDD18

USB_VD D33

3V3 1V8

Regulators

GND

PORT_1E

FLAG0

PORT_1F

FLAG1

USB

PHY

RXD[0..7]

RXRDY

CLK

TXD[0..7]

TXRDY OUT

TXRDY IN

VBUS

1-10uF

USB_DP

USB_DM

LINESTATE0

RXACTIVE

LINESTATE1

RXERROR

SWITCH

USB_SHIM_CFG

USB_ID

XnDnn

47K

220K

External

supply

100K (1V8 IO)

330K (3V3 IO)

Figure

Self powered

USB-device

When connecting a USB cable to the device it is possible an overvoltage transient will

be present on VBus due to the inductance of the USB cable combined with the required

input capacitor on VBus. The circuit in Figure

ensures that the transient does not

damage the device. The

k series resistor and -uF capacitor ensure than any input

transient is ltered and does not reach the device. A resistor to ground divides the V

VBUS voltage, and makes sure that the signal on the GPIO pin is not more than the IO

voltage. It should be

K for a .8V IO domain, or

K for a .V IO domain. The

resistor to ground is a bleeder resistor to discharge the input capacitor when VBus is not

present. The -uF input capacitor is required as part of the USB specication. A typical

value would be .uF to ensure the uF minimum requirement is met even under voltage

bias conditions.

In any case, extra components (such as a ferrite bead and diodes) may be required for

EMC compliance and ESD protection. Different wiring is required for USB-host and USB-

OTG.

Logical Core Requirements

The XMOS XUD library runs in a single logical core with endpoint and application cores

communicating with it via a combination of channel communication and shared memory

variables.

Each IN (host requests data from device) or OUT (data transferred from host to device)

endpoint requires one logical core.

MIPI PHY

The device has a two Data Lane MIPI D-PHY receiver on board, capable of receiving MIPI

data at up to . Gbps. The MIPI D-PHY has three differential pairs. By default, DP/DN

are lane one, DP/DN are the clock, and DP/DN are an optional second lane. The

lanes can be congured (and the lanes/clocks swapped around) using the MIPI lane

conguration register, see Appendix D.8.

The MIPI receiver has a decoder for common CSI- packed formats, and is connected to

the ports shown in Figure

. The MIPI block is clocked from its own clock source that

XM014035B Datasheet(PDF) 29 Page - Xmos Ltd.

XM014035B Datasheet(HTML) 29 Page - Xmos Ltd.

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