XM014035B datasheet(32/101 Pages) XMOS

32 / 101 page

XU6--FB6 Datasheet

capacitor and a ferrite of 6

ohm at

MHz and DCR < ohm, eg, Taiyo Yuden

BKHLM6-T) is recommended on this pin.

PLL_AVDD pins for the secondary PLL, with an associated PLL_AGND. This should

be ltered the same way as PLL_AVDD.

OTP_VCC pins for the OTP

A MIPI_VDD

pin for the analogue core supply to the MIPI D-PHY , with an asso-

ciated MIPI_GND. This supply needs a µF decoupler close to the pin. Connect

MIPI_VDD

to ground if MIPI is not used in the design.

A MIPI_VDD8 pin for the analogue .8V supply to the MIPI D-PHY. This supply needs

a µF decoupler close to the pin. Connect MIPI_VDD8 to ground if MIPI is not used

in the design.

A USB_VDD8 pin for the analogue .8V supply to the USB-PHY, with an associated

USB_GND8. You can leave USB_VDD8 unconnected if USB is not used in the design.

A USB_VDD pin for the analogue .V supply to the USB-PHY. You can leave USB_VDD

unconnected if USB is not used in the design.

GND for all other supplies, including VDD and VDDIO.

All ground pins must be connected directly to the board ground. The ground side of the

decoupling capacitors should have as short a path back to the GND pins as possible. A

bulk decoupling capacitor of at least

uF should be placed on VDD and VDDIO supplies.

The power supplies must be brought up monotonically and input voltages must not ex-

ceed specication at any time.

Power sequencing is summarised in Figure

. VDDIO and VDD can ramp up indepen-

dently. In order to reduce stresses on the device, it is preferable to make them ramp up

within a short time of each other, no more than

ms apart. You must ensure that the

VDDIOL, VDDIOT, and VDDIOR domains are valid before the device is taken out of reset,

as the boot pins are on VDDIOL. If you use a single .8V VDDIO power supply, then the

on-chip power-on-reset will ensure that reset stays low until all supplies are valid. If you

use multiple power supplies, then you must either ensure that RST_N stays asserted until

the VDDIOL/R/T domains are valid, or ensure that VDDIOL/R/T are valid by the time that

VDDIOB8 and VDD are valid.

Differential pair signal routing and placement

If you are using the USB PHY and/or the MIPI D-PHY , then you should route the differen-

tial pair marked D+ and D- carefully in order to ensure signal integrity. The D+ and D- lines

are the positive and negative data polarities of a high speed signal respectively. Their

high-speed differential nature implies that they must be coupled and properly isolated.

The board design must ensure that the board traces for D+ and D- are tightly matched.

In addition the differential impedance of D+ and D- must meet its specications. We

route MIPI D-PHY signals as loosely coupled pairs. Figures

and

show guidelines

on how to space and stack the board when routing differential pairs.

XM014035B Datasheet(PDF) 32 Page - Xmos Ltd.

XM014035B Datasheet(HTML) 32 Page - Xmos Ltd.

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