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XM014035B Datasheet(PDF) 26 Page - Xmos Ltd. |
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XM014035B Datasheet(HTML) 26 Page - Xmos Ltd. |
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26 / 101 page  XU6--FB6 Datasheet 0008 0000 0010 0000 Internal RAM FFF0 0000 FFF0 4000 Boot ROM 4000 0000 8000 0000 Software memory 1000 0000 2000 0000 External LPDDR1 RAM Figure : Address space xCORE0 LPDDR controller and PHY SRAM Execution pipeline 8-line buffer xCORE1 SRAM Execution pipeline 8-line buffer Address Data LPDDR memory device xCORE device Figure : LPDDR pin muxing. Logically, the memory can be connected to either Tile or Tile ; it is up to the program- mer to decide which one. The memory is connected by the tile enabling the external memory interface through a process-status control register, see Section B. . Only one tile should enable the external memory interface. A small buffer decouples the LPDDR memory from the device. The memory is addressed in the enabled device from address x - xFFF FFFF. |
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