XM014035B datasheet(81/101 Pages) XMOS

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XU6--FB6 Datasheet

Bits

Perm

Init

Description

Identier

Reserved

MIPI shim cong sel debug

MIPI_SHIM_CFG0_SEL_DEBUG

MIPI shim cong sel debug out

MIPI_SHIM_CFG0_SEL_DEBUG_OUT

Reserved

Set to to offset the output pixels with -x8 (for 8-bit outputs) or -

(for 6-bit outputs). This can be used to make unsigned data

signed around zero.

MIPI_SHIM_BIAS

Set to to add an extra data byte after every RGB6 or RGB888 pixel.

This will align pixels to a

-bit word.

MIPI_SHIM_DEMUX_STUFF

Species how the demultiplexer operates. The modes supported are

to6, to6, to6, rgb6to888, rgb888to888.

MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE

This eld needs to be set to the CSI- packet type that needs to be

demuxed. Only packets with a matching type are demultiplexed.

MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE

Reserved

Set to to enable the MIPI shim to demultiplex data according to the

demux mode and stuff elds. Demuxing is only applied to packets that

have the correct datatype.

MIPI_SHIM_CFG0_PIXEL_DEMUX_EN

xEF:

MIPI shim

conguration

LPDDR enable IID transactions

LPDDR_IID_ENABLE 0xC000

This register is used to enable one or more threads to route its requests through specied

queues. There are three queues (one read-only queue, RO, and two read-write queues,

RW/RW) and for each thread instruction accesses and data accesses can be routed

through specied queues.

Bits

Perm

Init

Description

Identier

Reserved

Two 8-bit masks, one bit per thread. Top eight bits enable instructions

to be routed through a specied queue, bottom eight bits enable data

to be routed through a specied queue.

LPDDR_IID_ENABLE

xC:

LPDDR enable

IID

transactions

LPDDR queue assignment for data

LPDDR_IID_0_7 0xC001

For each thread, this register species which queue a data access should be routed

through.

XM014035B Datasheet(PDF) 81 Page - Xmos Ltd.

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