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XM014035B Datasheet(PDF) 72 Page - Xmos Ltd. |
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XM014035B Datasheet(HTML) 72 Page - Xmos Ltd. |
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72 / 101 page  XU6--FB6 Datasheet This is achieved by running the PLL with a divider F for the rst part of the fractional period, and then F + 1 for the remainder of the period. The period is measured in input clocks divided by R + 1. Bits Perm Init Description Identier DW When set to , the secondary PLL will be a fractional N divided PLL SS_FRAC_N_ENABLE :6 RO - Reserved :8 DW The f value for the fractional divider. The number of clock cycles in the period that a divider F + 1 is used is f + 1. SS_FRAC_N_F_HIGH_CYC_CNT : DW The p value for the fractional divider. The period over which the frac- tional N divider oscillates between F and F + 1 is p + 1 SS_FRAC_N_PERIOD_CYC_CNT x: Secondary PLL Fractional N Divider D.8 LPDDR Controller conguration SS_LPDDR_CONTROLLER_CONFIG 0x13 Controls whether LPDDR Controller is enabled, and which core it is accessible to through the mux. Bits Perm Init Description Identier : RO - Reserved DW Denes which xCORE has access to the LPDDR controller via the mux SS_LPDDR_MUXTO_CORE1 DW When set to this will allow the LPDDR controller to access the pads SS_LPDDR_ENABLE x: LPDDR Controller conguration D. MIPI shim clock cong MIPI_CLK_DIVIDER 0x14 Congures the clock to the MIPI shim, the hardware block interfacing the MIPI PHY to the xCORE. Bits Perm Init Description Identier RW If set to , the secondary PLL is used as a source for the MIPI shim clock divider. By default, the output of the core PLL is used. SS_MIPI_CLK_FROM_APP_PLL : RO - Reserved 6 RW MIPI clock divider disable. When set to , the divider is enabled. SS_SSWITCH_MIPI_CLK_DIV_DISABLE : RW MIPI shim clock divider. When set to X the input clock is divided by 2(X + 1) . SS_SSWITCH_MIPI_CLK_DIV x: MIPI shim clock cong |
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