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FS32R274VBK2MMM Datasheet(PDF) 36 Page - NXP Semiconductors |
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FS32R274VBK2MMM Datasheet(HTML) 36 Page - NXP Semiconductors |
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36 / 78 page ![]() 7.3 DAC electrical specifications NOTE • All data is measured in single ended mode. Differential mode is guaranteed by design. • Specifications guaranteed only if factory trims are not overridden. Table 27. DAC parameters Symbol Parameter Condition Min Typ Max Unit NBIT Bits Base bits PWM bits — 12 4 (extra lsb's) — Bits SPSDAC Sample rate — — 10 — MSam ples/s DNL Linearity1 — -24 — 4 LSB Vout Output Voltage1, 2, 3 Single-Ended, Rl = 300 Ω 1.2 — 1.35 V Iout Full-Scale Output Current DAC full-scale adjust bits set to 01 or 10 4.0 — 4.5 mA NDAC DAC output noise 1, 4 @250 kHz @100 kHz @10 kHz @1 kHz — 20 30 65 170 nV/ sqrt(Hz ) SOE Static Offset Error1, 2 Single-Ended Differential with the full-scale adjust bits set to either 01 or 10 60 -30 75 0 100 30 mV TOE Transient Offset Error1, 2, 5 After low-pass filter and averaging — — 0.05 LSB tDV Transient Time Delay Variation 1, 2, 6 LSB step MSB step — — 1 10 ns Oc Output compliance single-ended, only the DNL specification is guaranteed. The TOE and Tdv may be degraded. 0 — 1.35 V tempco Temperature coefficient — –1 — 1.0 LSB/K 2 PSRR Power Supply Rejection Ratio7 Freq < 250 KHz 30 — — dB 1. DAC linearity, output swing, noise, TOE, and Tdv specifications are all based upon a 300 Ω DAC output load resistor and assume that the full-scale adjust bits are set to either 01 or 10. These specifications will NOT be met for other DAC output load resistor values. 2. Once all of the LVDs have cleared and the DAC is powered on, a one-time wait time of 300 ms is required before the DAC output signal is valid. 3. The full-scale DAC output is trimmed to 1.30 V ±10 mV with all DAC inputs set to 1 including both full-scale adjust bits. 4. Rl = 300 Ω, 10uF capacitor between Vdd_HV_DAC and DAC_C, ideal supply 5. Difference between ideal and real (Va+Vb/2), for all base and PWM LSBs 6. Falling edge to falling edge or rising edge to rising edge. Any transition DACn -> DACn + 1 Analog modules S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021 36 NXP Semiconductors |
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