FS32R274VBK2MMM datasheet(7/78 Pages) NXP

7 / 78 page

• Four data lanes, with up to 1 Gbps per lane and in total

• One clock lane

• Memory Protection

• Each core memory protection unit provides 24 entries

• Data and instruction bus system memory protection Unit (SMPU) with 16 region

descriptors each

• Register protection

• Clock Generation

• 40 MHz external crystal (XOSC)

• 16 MHz Internal oscillator (IRCOSC)

• Dual system PLL with one frequency modulated phase-locked loop (FMPLL)

• Low-jitter PLL to

ΣΔ-ADC and DAC clock generation

• Functional Safety

• Enables up to ASIL-D applications

• End to end ECC ensuring full protection of all data accesses throughout the

system, from each of the systems masters through the crossbar and into the

memories and peripherals

• FCCU for fault collection and fault handling

• MEMU for memory error management

• Safe eDMA controller

• User selectable Memory BIST (MBIST) can be enabled to run out of various

reset conditions or during runtime

• Self-Test Control Unit (STCU2)

• Error Injection Module (EIM)

• On-chip voltage monitoring

• Clock Monitor Unit (CMU) to support monitoring of critical clocks

• Security

• Cryptographic Security Engine (CSE2) enabling advanced security management

• Supports censorship and life-cycle management via Password and Device

Security (PASS) module

• Diary control for tamper detection (TDM)

• Support Modules

• Global Interrupt controller (INTC) capable of routing interrupts to any CPU

• Semaphore unit to manage access to shared resources

• Two CRC computation units with four polynomials

• 32-channel eDMA controller with multiple transfer request sources using

DMAMUX

• Boot Assist Module (BAM) supports internal flash programming via a serial link

(LIN / CAN)

• Timers

• Two Periodic Interval Timers (PIT) with 32-bit counter resolution

Introduction

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

FS32R274VBK2MMM Datasheet(PDF) 7 Page - NXP Semiconductors

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