FS32R274VBK2MMM datasheet(45/78 Pages) NXP

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9.1.4 MII/RMII Serial Management channel timing (MDC/MDIO)

The MDC/MDIO interface works at 3.3V compatible levels as mentioned in CMOS input

(vih/vil/voh/vol/)values in I/O pad DC electrical characteristics .

Ethernet works with maximum frequency of MDC at 2.5 MHz. Output pads configured

with SRC=11. MDIO pin must have external pull-up. Measurements are with input

transition of 1.0 ns and output load of 50 pF.

Table 36. Ethernet MDIO timing table

Num

Description

Min.

Max.

Unit

MDC00 MDC clock frequency

—

2.5

MHz

MDC10 MDC falling edge to MDIO

output invalid (minimum

propagation delay)

(-0.8 +

(ENET_MSCR[HOLDTIME]

+1)*(PBRIDGE_n_CLK period in

ns))

—

MDC11 MDC falling edge to MDIO

output valid (maximum

propagation delay)

—

(13 + (ENET_MSCR[HOLDTIME]

+1)*(PBRIDGE_n_CLK period in

ns))

MDC12 MDIO (input) to MDC rising

edge setup

—

MDC13 MDIO (input) to MDC rising

edge hold

—

MDC14 MDC pulse width high

40%

60%

MDC Period

MDC15 MDC pulse width low

40%

60%

MDC Period

MDC (output)

MDIO (output)

MDIO (input)

MDC10

MDC11

MDC12 MDC13

MDC14

MDC15

Figure 16. RMII/MII serial management channel timing diagram

Communication modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

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