FS32R274VBK2MMM datasheet(54/78 Pages) NXP

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Table 43. SPI timing (continued)

No.

Symbol

Parameter

Conditions

Min

Max

Unit

Master (MTFE = 1, CPHA = 0)9

-2 + N x SPI

IPG clock

period 10

—

Master (MTFE = 1, CPHA = 1)

–2

—

tSUO

Data valid (after SCK edge)

Master (MTFE = 0)

—

7 11

Slave

—

Master (MTFE = 1, CPHA = 0)12

—

7 + SPI IPG

Clock Period

Master (MTFE = 1, CPHA = 1)

—

tHO

Data hold time for outputs

Master (MTFE = 0)

–4 11

—

Slave

3.8

—

Master (MTFE = 1, CPHA = 0) 12

-4 + SPI IPG

Clock Period

—

Master (MTFE = 1, CPHA = 1)

–4

—

1. Slave Receive Only mode can operate at a maximum frequency of 60 MHz. In this mode, the SPI can receive data on SIN,

but no valid data is transmitted on SOUT.

2. For SPI_CTARn[PCSSCK] - 'PCS to SCK Delay Prescaler' configuration is '3' (01h) and SPI_CTARn[CSSCK] - 'PCS to

SCK Delay Scaler' configuration is '2' (0000h).

3. For SPI_CTARn[PASC] - 'After SCK Delay Prescaler' configuration is '3' (01h) and SPI_CTARn[ASC] - 'After SCK Delay

Scaler' configuration is '2' (0000h).

4. The numbers are valid when SPI is configured for 50/50. Refer the Reference manual for the mapping of the duty cycle to

each configuration. A change in duty cycle changes the parameter here. For example, a configuration providing duty cycle

of 33/66 at SPI translates to min tSCK/3 - 1.5 ns and max tSCK/3 + 1.5 ns.

5. The slave mode parameters (tSUI, tHI, tSUO and tHO) assume 50% duty cycle on SCK input. Any change in SCK duty cycle

input must be taken care during the board design or by the master timing.

6. The slave receive only mode parameters (tSUI and tHI) assume 50% duty cycle on SCK input. Any change in SCK duty

cycle input must be taken care during the board design or by the master timing. However, there is additional restriction in

the slave receive only mode that the duty cycle at the slave input should not go below tsdc(min) corresponding to the

tsdc(min) for the slave receive mode.

7. In the master mode, this is governed by tPCSSCK. Refer the SPI chapter in the Reference Manual for details. The minimum

spec is valid only for SPI_CTARn[PCSSCK]= '0b01' (PCS to SCK delay prescalar of 3) or higher.

8. In the master mode, this is governed by tPASC. Refer the SPI chapter in the Reference Manual for details. The minimum

spec is valid only for SPI_CTARn[PASC]= '0b01' (after SCK delay prescalar of 3) or higher.

9. For SPI_CTARn[BR] - 'Baud Rate Scaler' configuration is >= 4.

10. N = Configured sampling point value in MTFE=1 Mode.

11. Same value is applicable for PCS timing in continuous SCK mode.

12. SPI_MCR[SMPL_PT] should be set to 1.

NOTE

For numbers shown in the following figures, see Table 43.

Communication modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

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