FS32R274VBK2MMM datasheet(53/78 Pages) NXP

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6. Total lumped capacitance including silicon, package pin and bond wire. Application board simulation is needed to verify

LFAST template compliancy.

7. Absolute min = 0.15 V – (285 mV / 2) = 0 V

8. Absolute max = 1.6 V + (285 mV / 2) = 1.743 V

9. Total capacitance including silicon, package pin and bond wire

10. Total inductance including silicon, package pin and bond wire

9.4 Serial Peripheral Interface (SPI) timing specifications

The following table describes the SPI electrical characteristics.

MTEF=1 Mode timing values given below are only applicable when external SPI is in

classic mode. Slave mode timing values given below are applicable when device is in

MTFE=0.

• Measurements are with maximum output load of 50 pF, input transition of 1 ns and

pad configured as SRE = 11.

Table 43. SPI timing

No.

Symbol

Parameter

Conditions

Min

Max

Unit

tSCK

SPI cycle time

Master (MTFE = 0)

—

Master (MTFE = 1)

—

Slave (MTFE = 0)

—

Slave Receive Only mode1

—

tCSC

PCS to SCK delay

Master

63.82

—

tASC

After SCK delay

Master

68.83

—

tSDC

SCK duty cycle

Master4

tSCK/2 – 1

tSCK/2 + 1

Slave5

—

Slave Receive only mode6

tSCK/2 –

0.750

tSCK/2 +

0.750

Slave access time

SS active to SOUT valid

—

tDIS

Slave SOUT disable time

SS inactive to SOUT High-Z or invalid

—

tPCSC

PCSx to PCSS time

—

13 7

—

tPASC

PCSS to PCSx time

—

13 8

—

tSUI

Data setup time for inputs

Master (MTFE = 0)

—

Slave

—

Slave Receive Mode

—

Master (MTFE = 1, CPHA = 0)9

15-N x SPI

IPG clock

period10

—

Master (MTFE = 1, CPHA = 1)

—

tHI

Data hold time for inputs

Master (MTFE = 0)

–2

—

Slave

—

Slave Receive Mode

—

Table continues on the next page...

Communication modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

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