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FS32R274VBK2MMM Datasheet(PDF) 62 Page - NXP Semiconductors |
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FS32R274VBK2MMM Datasheet(HTML) 62 Page - NXP Semiconductors |
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62 / 78 page ![]() TCK Output Signals Input Signals Output Signals 11 12 13 14 15 Figure 35. JTAG boundary scan timing 10.2 Nexus Aurora debug port timing Table 47. Nexus Aurora debug port timing # Symbol Characteristic Min Max Unit 1 tREFCLK Reference clock frequency 625 1250 MHz 1a tMCYC Reference Clock rise/fall time — 400 ps 2 tRCDC Reference Clock Duty Cycle 45 55 % 3 JRC Reference Clock jitter — 40 ps 4 tSTABILITY Reference Clock Stability 50 — PPM 5 BER Bit Error Rate — 10-12 — 6 tEVTIPW EVTI Pulse Width 4.0 — tTCYC 7 JD Transmit lane Deterministic Jitter — 0.17 OUI 8 JT Transmit lane Total Jitter — 0.35 OUI Table continues on the next page... Debug modules S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021 62 NXP Semiconductors |
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