FS32R274VBK2MMM datasheet(41/78 Pages) NXP

41 / 78 page

Table 32. Flash read wait state and address pipeline control guidelines (continued)

Operating Frequency (fsys = SYS_CLK)

RWSC

APC

Flash read latency on

min-cache miss (# of

fcpu clock periods)

Flash read latency

on mini-cache hit (#

of fcpu clock

periods)

33 MHz < fsys <= 100 MHz

100 MHz < fsys <= 120 MHz

Communication modules

9.1 Ethernet switching specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

9.1.1 MII signal switching specifications

The following timing specs meet the requirements for MII style interfaces for a range of

transceiver devices.

• Measurements are with input transition of 1 ns and output load of 25 pF.

Table 33. MII signal switching specifications

Symbol

Description

Min.

Max.

Unit

—

RXCLK frequency

—

MHz

MII1

RXCLK pulse width high

35%

65%

RXCLK

period

MII2

RXCLK pulse width low

35%

65%

RXCLK

period

MII3

RXD[3:0], RXDV, RXER to RXCLK setup

—

MII4

RXCLK to RXD[3:0], RXDV, RXER hold

—

TXCLK frequency

—

MHz

MII5

TXCLK pulse width high

35%

65%

TXCLK

period

MII6

TXCLK pulse width low

35%

65%

TXCLK

period

MII7

TXCLK to TXD[3:0], TXEN, TXER invalid

—

MII8

TXCLK to TXD[3:0], TXEN, TXER valid

—

Communication modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

FS32R274VBK2MMM Datasheet(PDF) 41 Page - NXP Semiconductors

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