FS32R274VBK2MMM datasheet(44/78 Pages) NXP

44 / 78 page

Table 35. RGMII signal switching specifications

(continued)

Symbol

Description

Min

Typ

Max

Unit

Notes

Duty_G

Duty cycle for Gigabit

Duty_T

Duty cycle for 10/100T

Tr/Tf

Rise/fall time (20–80%)

—

1.5

1. For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.

2. For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an

additional trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100

the Max value is unspecified.

3. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as

long as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed

transitioned between.

TskewT

TskewR

TXD[3:0]

TXD[8:5]

TXD[7:4]

TXD[4]

TXEN

TXD[9]

TXERR

TXC (at transmitter)

TXD[n:0]

TX_CTL

TXC (at receiver)

Figure 14. RGMII transmit signal timing diagram

TskewT

TskewR

RXD[3:0]

RXD[8:5]

RXD[7:4]

RXD[4]

RXDV

RXD[9]

RXERR

RXC (at transmitter)

RXD[n:0]

RX_CTL

RXC (at receiver)

Figure 15. RGMII receive signal timing diagram

Communication modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

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