FS32R274VBK2MMM datasheet(40/78 Pages) NXP

40 / 78 page

Table 31. Flash memory AC timing specifications (continued)

Symbol

Characteristic

Min

Typical

Max

Units

tres

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

until DONE goes low.

—

100

tdone

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared.

—

tdones

Time from 1 to 0 transition on the MCR-EHV bit aborting a

program/erase until the MCR-DONE bit is set to a 1.

—

plus four

system

clock

periods

20.8

plus four

system

clock

periods

μs

tdrcv

Time to recover once exiting low power mode.

plus seven

system

clock

periods.

—

plus seven

system

clock

periods

μs

taistart

Time from 0 to 1 transition of UT0-AIE initiating a Margin Read

or Array Integrity until the UT0-AID bit is cleared. This time also

applies to the resuming from a suspend or breakpoint by

clearing AISUS or clearing NAIBP

—

taistop

Time from 1 to 0 transition of UT0-AIE initiating an Array

Integrity abort until the UT0-AID bit is set. This time also applies

to the UT0-AISUS to UT0-AID setting in the event of a Array

Integrity suspend request.

—

plus fifteen

system

clock

periods

tmrstop

Time from 1 to 0 transition of UT0-AIE initiating a Margin Read

abort until the UT0-AID bit is set. This time also applies to the

UT0-AISUS to UT0-AID setting in the event of a Margin Read

suspend request.

10.36

plus four

system

clock

periods

—

20.42

plus four

system

clock

periods

μs

8.6 Flash memory read wait-state and address-pipeline control

settings

The following table describes the recommended settings of the Flash Memory

Controller's PFCR1,2,3[RWSC] and PCRC1,2,3[APC] fields at various operating

frequencies, based on specified intrinsic flash memory access timed of the Flash memory.

Table 32. Flash read wait state and address pipeline control guidelines

Operating Frequency (fsys = SYS_CLK)

RWSC

APC

Flash read latency on

min-cache miss (# of

fcpu clock periods)

Flash read latency

on mini-cache hit (#

of fcpu clock

periods)

0 MHz < fsys <= 33 MHz

Table continues on the next page...

Memory modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

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