FS32R274VBK2MMM datasheet(48/78 Pages) NXP

48 / 78 page

Table 38. TxD output characteristics (continued)

Name

Description1

Min

Max

Unit

(=dCCTxD50% - 100 ns)

dCCTxDRISE25+dCCTx

DFALL25

Sum of Rise and Fall time of TxD signal at the output

—

dCCTxD01

Sum of delay between Clk to Q of the last FF and the final

output buffer, rising edge

—

dCCTxD10

Sum of delay between Clk to Q of the last FF and the final

output buffer, falling edge

—

1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +10%, TJ = –40 °C / 150°C, TxD pin load maximum 25 pF

dCCTxD10

dCCTxD01

TxD

PE_Clk

*FlexRay Protocol Engine Clock

Figure 20. FlexRay TxD signal propagation delays

9.2.3 RxD

Table 39. RxD input characteristic

Name

Description1

Min

Max

Unit

C_CCRxD

Input capacitance on RxD pin

—

uCCLogic_1

Threshold for detecting logic high

uCCLogic_0

Threshold for detecting logic low

dCCRxD01

Sum of delay from actual input to the D

input of the first FF, rising edge

—

dCCRxD10

Sum of delay from actual input to the D

input of the first FF, falling edge

—

1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +10%, TJ = –40 / 150 °C

Communication modules

S32R274/S32R264 Series Data Sheet, Rev. 6, 06/2021

NXP Semiconductors

FS32R274VBK2MMM Datasheet(PDF) 48 Page - NXP Semiconductors

FS32R274VBK2MMM Datasheet(HTML) 48 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Datasheet Download

Link URL