8.4 Layout

8.4.1 Layout Guidelines

Robust and reliable bus node design often requires the use of external transient protection devices to protect

against surge transients that may occur in industrial environments. Since these transients have a wide frequency

bandwidth (from approximately 3MHz to 300MHz), high-frequency layout techniques should be applied during

PCB design.

1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across

the board.

2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the

path of least impedance and not the path of least resistance.

3. Design the protection components into the direction of the signal path. Do not force the transient currents to

divert from the signal path to reach the protection device.

4. Apply 100nF to 220nF decoupling capacitors as close as possible to the VCC and VIO pins of transceiver,

UART and/or controller ICs on the board.

5. Use at least two vias for the ground connections of the decoupling capacitors at the power pins and the

protection devices to minimize the effective via inductance.

6. Use 1kΩ to 10kΩ pull-up and pull-down resistors for enable lines to limit noise currents in these lines during

transient events.

7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified

maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the

transceiver and prevent it from latching up.

8.4.2 Layout Example

1

2

3

4

5

10

9

8

7

6

D

DE

R

GND

SLR

A

B

VCC

VIO

RE

C

C

R

TVS

TVS

Via to ground

Via to VCC

MCU

R

R

GND

VIO

Figure 8-10. THVD2410V-EP, THVD2450V-EP (Half-Duplex) Layout Example

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THVD2410V-EP, THVD2450V-EP, THVD2452V-EP

SLLSFQ9B – MAY 2024 – REVISED OCTOBER 2024

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