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THVD2452VDREP Datasheet(PDF) 3 Page - Texas Instruments |
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THVD2452VDREP Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 40 page ![]() 4 Pin Configuration and Functions 1 VIO 2 R 3 DE 4 RE 5 D 6 GND 7 SLR 8 A 9 B 10 VCC Thermal Pad Not to scale Figure 4-1. THVD2410V-EP, THVD2450V-EP 10-Pin DRC Package (VSON) (Top View) 1 VIO 14 VCC 2 R 13 NC 3 RE 12 A 4 DE 11 B 5 D 10 Z 6 GND 9 Y 7 NC 8 SLR Not to scale Figure 4-2. THVD2452V-EP 14-Pin D Package (SOIC) (Top View) Table 4-1. Pin Functions NAME PIN NO. TYPE DESCRIPTION DRC D VIO 1 1 Logic Supply 1.65V to 5.5V supply for logic I/O signals R, RE, D, DE, and SLR) R 2 2 Digital Output Receive data output DE 3 4 Digital Input Driver enable input; integrated pull-down RE 4 3 Digital Input Receiver enable input; integrated pull-up D 5 5 Digital Input Transmission data input; integrated pull-up GND 6 6 Reference Potential Local device ground SLR 7 8 Digital Input Slew rate select ; integrated pull-down. For THVD2410V-EP: Low = 1Mbps, High = 250kbps. Defaults to 1Mbps if SLR is left floating. For THVD2450V-EP and THVD2452V-EP: Low = 50Mbps, High = 20Mbps. Defaults to 50Mbps if left floating. A 8 12 Bus Input Bus I/O (half-duplex), bus input (full-duplex) B 9 11 Bus Input Bus I/O (half-duplex), bus input (full-duplex) VCC 10 14 Bus Supply 3V to 5.5V supply for the transceiver Y - 9 Bus Output Bus output, Y Z - 10 Bus Output Bus output, Z NC - 7, 13 No connect pin. Internally not connected www.ti.com THVD2410V-EP, THVD2450V-EP, THVD2452V-EP SLLSFQ9B – MAY 2024 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: THVD2410V-EP THVD2450V-EP THVD2452V-EP |
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