5.11 Switching Characteristics - 50 Mbps

50-Mbps (THVD2450V-EP, THVD2452V-EP with SLR = 0 or floating) over recommended operating conditions. All typical

values are at 25°C and supply voltage of VCC = 5 V, VIO = 3.3 V, unless otherwise noted. (1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Driver

tr, tf

Differential output rise/fall time

VIO = 3 V to 3.6 V, VCC = 3 to 3.6

V, Typical at 3.3 V

RL = 54 Ω, CL = 50 pF

See Figure 6-3

1

5

7

ns

VCC = 4.5 to 5.5 V, Typical at 5 V

1

5

6

ns

tPHL, tPLH

Propagation delay

VIO = 3 V to 3.6 V, VCC = 3 to 3.6

V, Typical at 3.3 V

5

11

19

ns

VIO = 1.65 V to 1.95 V, VCC = 3 to

3.6 V, Typical at 3.3 V

7

12

22

ns

VIO = 3 V to 3.6 V, VCC = 4.5 to 5.5

V, Typical at 5 V

4

8

15

ns

VIO = 1.65 V to 1.95 V, VCC = 4.5

to 5.5 V, Typical at 5 V

6

10

19

ns

tSK(P)

Pulse skew, |tPHL – tPLH|

VCC = 3 to 3.6 V, Typical at 3.3 V

1

3

ns

VCC = 4.5 to 5.5 V, Typical at 5 V

1

3

ns

tPHZ, tPLZ

Disable time

RE = X

See Figure 6-4

and Figure 6-5

14

30

ns

tPZH, tPZL

Enable time

RE = 0 V ; VIO = 1.65 V to 1.95 V,

2.25 V to 2.75 V

20

35

ns

RE = 0 V ; VIO = 3 V to VCC V

15

32

ns

RE = VIO

2.5

4.5

μs

tSHDN

Time to shutdown

RE = VIO

50

500

ns

Receiver

tr, tf

Output rise/fall time

CL = 15 pF

See Figure 6-6

1.5

6

ns

tPHL, tPLH

Propagation delay

CL = 15 pF, VIO = 3 V to 3.6 V

See Figure 6-6

25

33

58

ns

tPHL, tPLH

Propagation delay

CL = 15 pF, VIO = 1.65 V to 1.95 V See Figure 6-6

25

35

60

ns

tSK(P)

Pulse skew, |tPHL – tPLH|

CL = 15 pF

See Figure 6-6

0.5

5

ns

tPHZ, tPLZ

Disable time

DE = X

12

25

ns

tPZH(1),

tPZL(1)

Enable time

DE = VIO

VIO = 1.65 V to 1.95 V,

See Figure 6-7

50

82

ns

VIO = 3 V to 3.6 V,

See Figure 6-7

50

75

ns

tPZH(2),

tPZL(2)

Enable time

DE = 0 V

See Figure 6-8

2.8

5

μs

tD(OFS)

Delay to enter fail-safe operation

CL = 15 pF

See Figure 6-9

7

10

18

μs

tD(FSO)

Delay to exit fail-safe operation

19

32

50

ns

tSHDN

Time to shutdown

DE = 0 V

See Figure 6-8

50

500

ns

(1)

A, B are driver output and receiver input terminals for Half duplex devices; A/B are Receiver input, Y/Z are driver output terminals for

Full duplex device

THVD2410V-EP, THVD2450V-EP, THVD2452V-EP

SLLSFQ9B – MAY 2024 – REVISED OCTOBER 2024

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12

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