S29GL01GP10FFIR12 datasheet(75/77 Pages) SPANSION

75 / 77 page

November 8, 2007 S29GL-P_00_A7

S29GL-P MirrorBit® Flash Family

Da ta

Shee t

(Prelim i nar y )

13. Advance Information on S29GL-R 65 nm MirrorBit Hardware

Reset (RESET#) and Power-up Sequence

Note

CE#, OE# and WE# must be at logic high during Reset Time.

Figure 13.1 Reset Timings

Note

The sum of tRP and tRH must be equal to or greater than tRPH.

Notes

1. VIO < VCC + 200 mV.

2. VIO and VCC ramp must be in sync during power-up. If RESET# is not stable for 500 µs, the following conditions may occur: the device

does not permit any read and write operations, valid read operations return FFh, and a hardware reset is required.

3. Maximum VCC power up current is 20 mA (RESET# =VIL).

Figure 13.2 Power-On Reset Timings

Note

The sum of tRP and tRH must be equal to or greater than tRPH.

Table 13.1 Hardware Reset (RESET#)

Parameter

Description

Limit

Time

Unit

tRPH

RESET# Low to CE# Low

Min

µs

tRP

RESET# Pulse Width

Min

200

tRH

Time between RESET# (high) and CE# (low)

Min

200

Table 13.2 Power-Up Sequence Timings

Parameter

Description

Limit

Time

Unit

tVCS

VCC Setup Time to first access

Min

300

µs

tVIOS

VIO Setup Time to first access

Min

300

µs

tRPH

RESET# Low to CE# Low

Min

µs

tRP

RESET# Pulse Width

Min

200

tRH

Time between RESET# (high) and CE# (low)

Min

200

tRPH

CE#

RESET#

tRP

tRH

CE#

VCC

V IO

RESET#

t VIOS

t VCS

t RP

t RH

t RPH

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