TMP89FS60 datasheet(37/410 Pages) TOSHIBA

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Page 23

TMP89FS60

RA001

The main system clock (fm) is generated from the gear clock (fcgck). Therefore, the machine cycle time

is 1/fcgck [s].

The gear clock (fcgck) is generated from the high-frequency clock (fc).

In the single-clock mode, the low-frequency clock generation circuit pins P03 (XTIN) and P04

(XTOUT) can be used as the I/O ports.

(1)

NORMAL1 mode

In this mode, the CPU core and the peripheral circuits operate using the gear clock (fcgck).

The NORMAL1 mode becomes active after reset release.

(2)

IDLE1 mode

In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the

gear clock (fcgck).

The IDLE1 mode is activated by setting SYSCR2<IDLE> to "1" in the NORMAL1 mode.

When the IDLE1 mode is activated, the CPU and the watchdog timer stop.

When the interrupt latch enabled by the interrupt enable register EFR becomes "1", the IDLE1

mode is released to the NORMAL1 mode.

When the IMF (interrupt master enable flag) is "1" (interrupts enabled), the operation returns nor-

mal after the interrupt processing is completed.

When the IMF is "0" (interrupts disabled), the operation is restarted by the instruction that follows

the IDLE1 mode activation instruction.

(3)

IDLE0 mode

In this mode, the CPU and the peripheral circuits stop, except the oscillation circuits and the time

base timer.

In the IDLE0 mode, the peripheral circuits stop in the states when the IDLE0 mode is activated or

become the same as the states when a reset is released. For operations of the peripheral circuits in the

IDLE0 mode, refer to the section of each peripheral circuit.

The IDLE0 mode is activated by setting SYSCR2<TGHALT> to "1" in the NORMAL1 mode.

When the IDLE0 mode is activated, the CPU stops and the timing generator stops the clock supply

to the peripheral circuits except the time base timer.

When the falling edge of the source clock selected at TBTCR<TBTCK> is detected, the IDLE0

mode is released, the timing generator starts the clock supply to all the peripheral circuits and the

NORMAL1 mode is restored.

Note that the IDLE0 mode is activated and restarted, regardless of the setting of

TBTCR<TBTEN>.

When the IDLE0 mode is activated with TBTCR<TBTEN> set at "1", the INTTBT interrupt latch

is set after the NORMAL mode is restored.

When the IMF is "1" and the EF5 (the individual interrupt enable flag for the time base timer) is

"1", the operation returns normal after the interrupt processing is completed.

When the IMF is "0" or when the IMF is "1" and the EF5 (the individual interrupt enable flag for

the time base timer) is "0", the operation is restarted by the instruction that follows the IDLE0 mode

activation instruction.

TMP89FS60 Datasheet(PDF) 37 Page - Toshiba Semiconductor

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