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TMP89FS60 Datasheet(PDF) 45 Page - Toshiba Semiconductor

Part # TMP89FS60
Description  8 Bit Microcontroller
PDF  410 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP89FS60 Datasheet(HTML) 45 Page - Toshiba Semiconductor

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Page 31
TMP89FS60
RA001
Note: When the operation returns to the NORMAL2 mode, fc is input to the frequency division circuit of the warm-up counter.
2.3.6.2
IDLE1/2 and SLEEP1 modes
The IDLE1/2 and SLEEP1 modes are controlled by the system control register 2 (SYSCR2) and
maskable interrupts. The following states are maintained during these modes.
1. The CPU and the watchdog timer stop their operations. The peripheral circuits continue to oper-
ate.
2. The data memory, the registers, the program status word and the port output latches are all held
in the status in effect before IDLE1/2 or SLEEP1 mode was started.
3. The program counter holds the address of the instruction 2 ahead of the instruction which starts
the IDLE1/2 or SLEEP1 mode.
Table 2-4
Oscillation Start Operation at Release of the STOP Mode
Operation mode before the STOP
mode is started
High-frequency
clock
Low-frequency
clock
Oscillation start operation after release
Single-clock
mode
NORMAL1
High-frequency
clock oscillation
circuit
-
The high-frequency clock oscillation circuit starts
oscillation.
The low-frequency clock oscillation circuit stops
oscillation.
Dual-clock mode
NORMAL2
High-frequency
clock oscillation
circuit
Low-frequency
clock oscillation cir-
cuit
The high-frequency clock oscillation circuit starts
oscillation.
The low-frequency clock oscillation circuit starts
oscillation.
SLOW1
-
Low-frequency
clock oscillation cir-
cuit
The high-frequency clock oscillation circuit stops
oscillation.
The low-frequency clock oscillation circuit starts
oscillation.



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