TMP89FS60 datasheet(51/410 Pages) TOSHIBA

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Page 37

TMP89FS60

RA001

Figure 2-13 Switching the Main System Clock (fm) (Switching from fs/4 to fcgck)

Example : Switching from the SLOW1 mode to the NORMAL1 mode after the stability of the high-frequency clock oscilla-

tion circuit is confirmed at the warm-up counter (fc = 8 MHz, warm-up time = 4.0 ms)

; #### Initialize routine ####

SET

(P0FC).2

; P0FC2 = 1

(Uses P02/03 as oscillators)

(WUCCR), 0x09

; WUCCR<WUCDIV> = 10 (Divided by 2)

WUCCR<WUCSEL> = 0 (Selects fc as the source clock)

(WUCDR), 0x7D

; Sets the warm-up time

(Determine the time depending on the frequency and the oscillator

characteristics)

4ms / 32us = 125

→ 0x7D

SET

(EIRL). 4

; Enables INTWUC interrupts

SET

(SYSCR2) .6

; SYSCR2<XEN> = 1

(Starts the oscillation of the high-frequency clock oscillation circuit)

; #### Interrupt service routine of warm-up counter interrupts ####

PINTWUC:

CLR

(SYSCR2). 4

; SYSCR2<SYSCK> = 0

(Switches the main system clock to the gear clock)

NOP

; Waits for 2 machine cycles

NOP

CLR

(SYSCR2). 5

; SYSCR2<XTEN> = 0

(Turns off the low-frequency clock oscillation circuit)

RETI

VINTWUC:

PINTWUC

; INTWUC vector table

Gear clock (fcgck)

When the rising edge of fs/4 is

detected twice after SYSCR2<SYSCK>

is changed from 1 to 0, f is stopped

for synchronization.

When the rising edge of fcgck is detected

twice after fm is stopped, fm is switched to fcgck.

Quarter of the low-frequency clock

(fs/4)

Main system clock

SYSCR2<SYSCK>

2.5/fcgck(max.)

TMP89FS60 Datasheet(PDF) 51 Page - Toshiba Semiconductor

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