TMP89FS60 datasheet(90/410 Pages) TOSHIBA

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Page 76

5. Watchdog Timer (WDT)

5.3 Functions

TMP89FS60

RA000

Note:The 8-bit up counter source clock operates out of synchronization with WDCTR<WDTEN>. Therefore, the first

overflow time of the 8-bit up counter after WDCTR<WDTEN> is set to "1" may get shorter by a maximum of 1

source clock. The 8-bit up counter must be cleared within the period of the overflow time minus 1 source clock

cycle.

5.3.2

Setting the clear time of the 8-bit up counter

WDCTR<WDTW> sets the clear time of the 8-bit up counter.

When WDCTR<WDTW> is "00", the clear time is equal to the overflow time of the 8-bit up counter, and the

8-bit up counter can be cleared at any time.

When WDCTR<WDTW> is not "00", the clear time is fixed to only a certain period within the overflow

time of the 8-bit up counter. If the operation for releasing the 8-bit up counter is attempted outside the clear

time, a watchdog timer interrupt request signal occurs.

At this time, the watchdog timer is not cleared but continues counting. If the 8-bit up counter is not cleared

within the clear time, a watchdog timer reset request signal or a watchdog timer interrupt request signal occurs

due to the overflow, depending on the WDCTR<WDTOUT> setting.

Figure 5-3 WDCTR<WDTW> and the 8-bit up Counter Clear Time

5.3.3

Setting the overflow time of the 8-bit up counter

WDCTR<WDTT> sets the overflow time of the 8-bit up counter.

When the 8-bit up counter overflows, a watchdog timer reset request signal or a watchdog timer interrupt

request signal occurs, depending on the WDCTR<WDTOUT> setting.

If the watchdog timer interrupt request signal is selected as the malfunction detection signal, the watchdog

counter continues counting, even after the overflow has occurred.

The watchdog timer temporarily stops counting up in the STOP mode (including warm-up) or in the IDLE/

SLEEP mode, and restarts counting up after the STOP/IDLE/SLEEP mode is released. To prevent the 8-bit up

counter from overflowing immediately after the STOP/IDLE/SLEEP mode is released, it is recommended to

clear the 8-bit up counter before the operation mode is changed.

Table 5-1

Watchdog Timer Overflow Time (fcgck=8.0 MHz; fs=32.768 kHz)

WDTT

Watchdog timer overflow time [s]

NORMAL mode

SLOW

mode

DV9CK = 0

DV9CK = 1

32.77 m

62.50 m

131.07 m

250.00 m

524.29 m

1.000

2.097

4.000

When WDCTR<WDTW> is 00

8-bit up counter value

When WDCTR<WDTW> is 01

When WDCTR<WDTW> is 10

When WDCTR<WDTW> is 11

00H

01H

3FH 40H

7FH 80H

BFH C0H

FFH 00H

FFH

Clear time

Outside the clear time

Clear time

Outside the clear time

Clear time

Outside the clear time

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