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TMP89FS60 Datasheet(PDF) 67 Page - Toshiba Semiconductor |
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TMP89FS60 Datasheet(HTML) 67 Page - Toshiba Semiconductor |
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67 / 410 page  Page 53 TMP89FS60 RA003 Note 1: Do not set the IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 2: In the main program, before manipulating the interrupt enable flag (EF), be sure to clear the master enable flag (IMF) to "0" (Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the EF (Enable interrupt by EI instruction) In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. However, if using multiple interrupt in the interrupt service routine, manipulate the EF before setting the IMF to "1". Note 3: When a read instruction is executed on EIRL, bits 3 to 1 are read as "0". Other unused bits are read as "0". Interrupt enable register (EIRL) EIRL 76543 210 (0x003A) Bit Symbol EF7 EF6 EF5 EF4 - - - IMF Read/Write R/W R/W R/W R/W R R R R/W After reset 00000 000 Function INTTXD0 INTRXD0 / INTSIO0 INTTBT INTWUC Interrupt master en- able flag Interrupt enable register (EIRH) EIRH 76543 210 (0x003B) Bit Symbol EF15 EF14 EF13 EF12 EF11 EF10 EF9 EF8 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 00000 000 Function INTSBI0/ INTSIO0 INTTCA0 INTTC01 INTTC00 INTRTC INTADC INTVLTD INT5 Interrupt enable register (EIRE) EIRE 76543 210 (0x003C) Bit Symbol EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W After reset 00000 000 Function INTTXD1 INTRXD1/ INTSIO1 INTTCA1 INT4 INT3 INT2 INT1 INT0 Interrupt enable register (EIRD) EIRD 76543 210 (0x003D) Bit Symbol ---- EF27 EF26 EF25 EF24 Read/Write RRRR R/W R/W R/W R/W After reset 00000 000 Function INTTXD2 INTRXD2 INTTC03 INTTC02 EF27 to EF4 Individual interrupt enable flag (Specified for each bit) 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. IMF Interrupt master enable flag 0: 1: Disables the acceptance of all maskable interrupts. Enables the acceptance of all maskable interrupts. |
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