TMP89FS60 datasheet(53/410 Pages) TOSHIBA

53 / 410 page

Page 39

TMP89FS60

RA001

Note 3: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in

NORMAL1 mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unex-

pected timing.

Note 4: Bits 7 to 3 of SYSCR3 are read as "0".

Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit opera-

tion.

Note 2: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in NORMAL

mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unexpected tim-

ing.

Note 3: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode

when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing.

Note 1: The enabled SYSCR3<RSTDIS> is initialized by a power-on reset only, and cannot be initialized by any other reset sig-

nals. The value written in SYSCR3 is reset by a power-on reset and other reset signals.

Note 2: Bits 7 to 3 of SYSCR4 are read as "0".

System control register 4

SYSCR4

(0x0FDF)

76543

210

Bit Symbol

SYSCR4

Read/Write

After reset

00000

000

SYSCR4

Writes the SYSCR3 data control code.

0xB2 : Enables the contents of SYSCR3<RSTDIS>.

0xD4 : Enables the contents of SYSCR3<RAREA> and SYSCR3

<RVCTR>.

0x71 : Enables the contents of IRSTSR<FCLR>

Others : Invalid

System control status register 4

SYSSR4

(0x0FDF)

76543

210

Bit Symbol

-----

(RVCTRS)

(RAREAS)

RSTDISS

Read/Write

RRRRRRRR

After reset

00000

000

RSTDISS

External reset input enable status

0 : The enabled SYSCR3<RSTDIS> data is "0".

1 : The enabled SYSCR3<RSTDIS> data is "1".

Internal factor reset detection status register

IRSTSR

(0x0FCC)

76543

210

Bit Symbol

FCLR

FLSRF

TRMDS

TRMRF

LVD2RF

LVD1RF

SYSRF

WDTRF

Read/Write

RRRRRRR

After reset

00000

000

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