TMP89FS60 datasheet(64/410 Pages) TOSHIBA

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3. Interrupt Control Circuit

3.2 Interrupt Latches (IL27 to IL3)

TMP89FS60

RA003

3.2

Interrupt Latches (IL27 to IL3)

An interrupt latch is provided for each interrupt source, except for a software interrupt and an undefined instruc-

tion execution interrupt. When an interrupt request is generated, the latch is set to "1", and the CPU is requested to

accept the interrupt if its acceptance is enabled. The interrupt latch is cleared to "0" immediately after the interrupt is

accepted. All interrupt latches are initialized to "0" during reset.

The interrupt latches are located at addresses 0x0FE0, 0x0FE1, 0x0FE2, 0x0FE3 in SFR area. Each latch can be

cleared to "0" individually by an instruction. However, IL2 and IL3 interrupt latches cannot be cleared by instruc-

tions.

Do not use any read-modify-write instruction, such as a bit manipulation or operation instruction, because it may

clear interrupt requests generated while the instruction is executed.

Interrupt latches cannot be set to "1" by using an instruction. Writing "1" to an interrupt latch is equivalent to deny-

ing clearing of the interrupt latch, and not setting the interrupt latch.

Since interrupt latches can be read by instructions, the status of interrupt requests can be monitored by software.

Note: In the main program, before manipulating an interrupt latch (IL), be sure to clear the master enable flag (IMF) to "0"

(Disable interrupt by DI instruction). Then set the IMF to "1" as required after operating the IL (Enable interrupt by EI

instruction).

In the interrupt service routine, the IMF becomes "0" automatically and need not be cleared to "0" normally. How-

ever, if using multiple interrupt in the interrupt service routine, manipulate the IL before setting the IMF to "1".

Example 1: Clears interrupt latches

; IMF

← 0

(ILL), 0y00111111

; IL7 to IL6

← 0

(ILH), 0y11101000

; IL12, IL10 to IL8

← 0

; IMF

← 1

Example 2: Reads interrupt latches

WA, (ILL)

; W

← ILH, A ← ILL

Example 3: Tests interrupt latches

TEST

(ILL). 7

; if IL7=1 then jump

F, SSET

;

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