TMP89FS60 datasheet(42/410 Pages) TOSHIBA

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Page 28

2. CPU Core

2.3 System clock controller

TMP89FS60

RA001

2. Release by key-on wakeup

3. Release by the voltage detection circuits

Note: During the STOP period (from the start of the STOP mode to the end of the warm-up), due to

changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may

be accepted immediately after the STOP mode is released. Before starting the STOP mode,

therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear

unnecessary interrupt latches.

1. Release by the STOP pin

Release the STOP mode by using the STOP pin.

To release the STOP mode by using the STOP pin, set VDCR2<VDSS> to "00" or "10".

(For details of VDCR2, refer to the section of voltage detection circuits.)

The STOP mode release by the STOP pin includes the level-sensitive release mode and the

edge-sensitive release mode, either of which can be selected at SYSCR1<RELM>.

The STOP pin is also used as the P11 port and the INT5 (external interrupt input 5) pin.

Note: When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the

main system clock when the STOP mode was started, regardless of WUCCR<WUCSEL>.

- Level-sensitive release mode

The STOP mode is released by setting the STOP pin high.

Setting SYSCR1<RELM> to "1" selects the level-sensitive release mode.

This mode is used for the capacitor backup when the main power supply is cut off and

the long term battery backup.

Even if an instruction for starting the STOP mode is executed while the STOP pin in-

put is high, the STOP mode does not start. Thus, to start the STOP mode in the level-

sensitive release mode, it is necessary for the program to first confirm that the STOP pin

input is low.

This can be confirmed by testing the port by the software or using interrupts

Note:

When the STOP mode is released, the warm-up counter source clock automatically changes

to the clock that generated the main system clock when the STOP mode was started, regard-

less of WUCCR<WUCSEL>.

Example: Starting the STOP mode from the SLOW mode with an INT5 interrupt

(Warm-up time at release of the STOP mode is about 450ms at fs=32.768 KHz.)

PINT5:

TEST

(P0PRD).5

; To reject noise, the STOP mode does not start

JRS

F, SINT5

; if the STOP pin input is high.

(SYSCR1), 0x40

; Sets up the level-sensitive release mode

(WUCCR), 0x03

; WUCCR<WUCDIV> = 00 (No division) (Note)

(WUCDR),0xE8

;

Sets the warm-up time

450 ms/1.953 ms = 230.4

→ round up to 0xE8

; IMF = 0

SET

(SYSCR1).7

; Starts the STOP mode

SINT5:

RETI

STOP pin

XOUT pin

NORMAL mode

The STOP mode is released by the hardware.

NORMAL mode

VIH

Warm-up

STOP mode

Confirm by program that

the STOP pin input is low

and start the STOP mode.

Always released if the

STOP pin input is high.

TMP89FS60 Datasheet(PDF) 42 Page - Toshiba Semiconductor

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