TMP89FS60 datasheet(57/410 Pages) TOSHIBA

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Page 43

TMP89FS60

RA001

2.4.4.2

Power-on reset

The power-on reset is an internal factor reset that occurs when the power is turned on.

When power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage

of the power-on reset circuit, a reset signal is generated and if it is higher than the releasing voltage of the

power-on reset circuit, a reset signal is released.

When power supply voltage goes down, if the supply voltage is equal to or lower than the detecting

voltage of the power-on reset circuit, a reset signal is generated.

Refer to "Power-on Reset circuit".

2.4.4.3

Voltage detection reset

The voltage detection reset is an internal factor reset that occurs when it is detected that the supply volt-

age has reached a predetermined detection voltage.

Refer to "Voltage Detection Circuit".

2.4.4.4

Watchdog timer reset

The watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog timer

is detected.

Refer to "Watchdog Timer".

2.4.4.5

System clock reset

The system clock reset is an internal factor reset that occurs when it is detected that the oscillation

enable register is set to a combination that puts the CPU into deadlock.

Refer to "Clock Control Circuit".

2.4.4.6

Trimming data reset

The trimming data reset is an internal factor reset that occurs when the trimming data latched in the

internal circuit is broken down during operation due to noise or other factors.

The trimming data is a data bit provided for adjustment of the ladder resistor that generates the compar-

ison voltage for the power-on reset and the voltage detection circuits.

This bit is loaded from the non-volatile exclusive use memory during the warm-up time that follows

reset release (tPWUP) and latched into the internal circuit.

If the trimming data loaded from the non-volatile exclusive use memory during the warm-up operation

that follows reset release is abnormal, IRSTSR<TRMDS> is set to "1".

When IRSTSR<TRMDS> is read as "1" in the initialize routine immediately after reset release, the

trimming data need to be reloaded by generating an internal factor reset, such as a system clock reset, and

activating the warm-up operation again.

If IRSTSR<TRMDS> is still set to "1" after repeated reading, the detection voltage of the voltage detec-

tion circuit and power-on reset circuit does not satisfy the characteristic specified in the electric character-

istics. Design the system so that the system will not be damaged in such a case.

2.4.4.7

Flash standby reset

The flash standby reset is an internal factor reset generated by the reading or writing of data of the flash

memory while it is on standby.

Refer to "Flash Memory".

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