TMP89FS60 datasheet(78/410 Pages) TOSHIBA

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Page 64

4. External Interrupt control circuit

4.2 Control

TMP89FS60

RA000

4.2

Control

External interrupts are controlled by the following registers:

Note 1: Clearing INTxEN(x=0 to 5) to "0" stops the clock supply to the external interrupts. This invalidates the data written

in the control register for each external interrupt. When using the external interrupts, set INTxEN to "1" and then

write data into the control register for each external interrupt.

Note 2: Interrupt request signals may be generated when INTxEN is changed. Before changing INTxEN, clear the corre-

sponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is

changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed

and clear the interrupt latch. And when the operation mode is changed from SLOW1/2 or SLEEP1 to NORMAL1/

2 or IDLE1/2, wait 2/fcgck+3/fspl [s] after the operation mode is changed and clear the interrupt latch.

Note 3: Bits 7 and 6 of POFFSET3 are read as "0".

Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz]

Note 2: Interrupt requests may be generated during transition of the operation mode. Before changing the operation mode, clear

the corresponding interrupt enable register to "0" to disable the generation of interrupt. When the operation mode is

changed from NORMAL1/2 or IDLE1/2 to SLOW1/2 or SLEEP1, wait 12/fs [s] after the operation mode is changed and

Low power consumption register 3

POFFCR3

76543

210

(0x0F77)

Bit Symbol

INT5EN

INT4EN

INT3EN

INT2EN

INT1EN

INT0EN

Read/Write

R/W

After reset

00000

000

INT5EN

INT5 control

Disable

Enable

INT4EN

INT4 control

Disable

Enable

INT3EN

INT3 control

Disable

Enable

INT2EN

INT2 control

Disable

Enable

INT1EN

INT1 control

Disable

Enable

INT0EN

INT0 control

Disable

Enable

External interrupt control register 1

EINTCR1

(0x0FD8)

76543

210

Bit Symbol

INT1LVL

INT1ES

INT1NC

Read/Write

RRRR

R/W

After reset

0000

INI1LVL

Noise canceller pass signal level

when the interrupt request signal is

generated for external interrupt 1

0 :

1 :

Initial state or signal level "L"

Signal level "H"

INT1ES

Selects the interrupt request gener-

ating condition for external interrupt

00 :

01 :

10 :

11 :

An interrupt request is generated at the rising edge of the noise canceller

pass signal

An interrupt request is generated at the falling edge of the noise canceller

pass signal

An interrupt request is generated at both edges of the noise canceller

pass signal

Reserved

INT1NC

Sets the noise canceller sampling

interval for external interrupt 1

NORMAL1/2, IDLE1/2

SLOW1/2, SLEEP1

00 :

01 :

10 :

11 :

fcgck [Hz]

fcgck / 22 [Hz]

fcgck / 23 [Hz]

fcgck / 24 [Hz]

00 :

01 :

10 :

11 :

fs/4 [Hz]

TMP89FS60 Datasheet(PDF) 78 Page - Toshiba Semiconductor

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