TMP89FS60 datasheet(47/410 Pages) TOSHIBA

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Page 33

TMP89FS60

RA001

(1)

Start the IDLE1/2 and SLEEP1 modes

After the interrupt master enable flag (IMF) is set to "0", set the individual interrupt enable flag

(EF) to "1", which releases IDLE1/2 and SLEEP1 modes.

To start the IDLE1/2 or SLEEP1 mode, set SYSCR2<IDLE> to "1".

If the release condition is satisfied when it is attempted to start the IDLE1/2 or SLEEP1 mode,

SYSCR2<IDLE> remains cleared and the IDLE1/2 or SLEEP1 mode will not be started.

Note 1: When a watchdog timer interrupt is generated immediately before the IDLE1/2 or SLEEP1 mode

is started, the watchdog timer interrupt will be processed but the IDLE1/2 or SLEEP1 mode will

not be started.

Note 2: Before starting the IDLE1/2 or SLEEP1 mode, enable the interrupt request signals to be gener-

ated to release the IDLE1/2 or SLEEP1 mode and set the individual interrupt enable flag.

(2)

Release the IDLE1/2 and SLEEP1 modes

The IDLE1/2 and SLEEP1 modes include a normal release mode and an interrupt release mode.

These modes are selected at the interrupt master enable flag (IMF). After releasing IDLE1/2 or

SLEEP1 mode, SYSCR2<IDLE> is automatically cleared to "0" and the operation mode is returned

to the mode preceding the IDLE1/2 or SLEEP1 mode.

The IDLE1/2 and SLEEP1 modes are also released by a reset by the RESET pin, a power-on reset

and a reset by the voltage detection circuits. After releasing the reset, the warm-up starts. After the

warm-up is completed, the NORMAL1 mode becomes active.

• Normal release mode (IMF = "0")

The IDLE1/2 or SLEEP1 mode is released when the interrupt latch enabled by the individ-

ual interrupt enable flag (EF) is "1". The operation is restarted by the instruction that follows

the IDLE1/2 or SLEEP1 mode start instruction. Normally, the interrupt latch (IL) of the inter-

rupt source used for releasing must be cleared to "0" by load instructions.

• Interrupt release mode (IMF = "1")

The IDLE1/2 or SLEEP1 mode is released when the interrupt latch enabled by the individ-

ual interrupt enable flag (EF) is "1". After the interrupt is processed, the operation is restarted

by the instruction that follows the IDLE1/2 or SLEEP1 mode start instruction.

2.3.6.3

IDLE0 and SLEEP0 modes

The IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time

base timer control register (TBTCR). The following states are maintained during the IDLE0 and SLEEP0

modes:

• The timing generator stops the clock supply to the peripheral circuits except the time base timer.

• The data memory, the registers, the program status word and the port output latches are all held in

the states in effect before the IDLE0 or SLEEP0 mode was started.

• The program counter holds the address of the instruction 2 ahead of the instruction which starts

the IDLE0 or SLEEP0 mode.

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