TMP89FS60 datasheet(88/410 Pages) TOSHIBA

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Page 74

5. Watchdog Timer (WDT)

5.2 Control

TMP89FS60

RA000

Note 1: fcgck, Gear clock [Hz]; fs, Low frequency clock [Hz]

Note 2: WDCTR<WDTW>, WDCTR<WDTT> and WDCTR<WDTOUT> cannot be changed when WDCTR<WDTEN> is "1". If

WDCTR<WDTEN> is "1", clear WDCTR<WDTEN> to "0" and write the disable code (0xB1) into WDCDR to disable the

watchdog timer operation. Note that WDCTR<WDTW>, WDCTR<WDTT> and WDCTR<WDTOUT> can be changed at

the same time as setting WDCTR<WDTEN> to "1".

Note 3: Bit 7 and bit 6 of WDCTR are read as "1" and "0" respectively.

Note: WDCDR is a write-only register and must not be accessed by using a read-modify-write instruction, such as a bit operation.

WDTEN

Enables/disables the watchdog

timer operation.

0 :

1 :

Disable

Enable

WDTW

Sets the clear time of the 8-bit up

counter.

00 :

01 :

10 :

11 :

The 8-bit up counter is cleared by writing the clear code at any point within

the overflow time of the 8-bit up counter.

A watchdog timer interrupt request is generated by writing the clear code

at a point within the first quarter of the overflow time of the 8-bit up

counter. The 8-bit up counter is cleared by writing the clear code after the

first quarter of the overflow time has elapsed.

A watchdog timer interrupt request is generated by writing the clear code

at a point within the first half of the overflow time of the 8-bit up counter.

The 8-bit up counter is cleared by writing the clear code after the first half

of the overflow time has elapsed.

A watchdog timer interrupt request is generated by writing the clear code

at a point within the first three quarters of the overflow time of the 8-bit up

counter. The 8-bit up counter is cleared by writing the clear code after the

first three quarters of the overflow time have elapsed.

WDTT

Sets the overflow time of the 8-bit

up counter.

NORMAL mode

SLOW mode

DV9CK=0

DV9CK=1

00 :

218/fcgck

211/fs

01:

220/fcgck

213/fs

10:

222/fcgck

215/fs

11:

224/fcgck

217/fs

WDTOUT

Selects an overflow detection signal

of the 8-bit up counter.

0 :

1 :

Watchdog timer interrupt request signal

Watchdog timer reset request signal

Watchdog timer control code register

WDCDR

(0x0FD5)

76543

210

Bit Symbol

WDTCR2

Read/Write

After reset

00000

000

WDTCR2

Writes watchdog timer control

codes.

0x4E :

0xB1 :

Others :

Clears the watchdog timer. (Clear code)

Disables the watchdog timer operation and clears the 8-bit up

counter when WDCTR<WDTEN> is "0". (Disable code)

Invalid

8-bit up counter monitor

WDCNT

(0x0FD6)

76543

210

Bit Symbol

WDCNT

Read/Write

After reset

00000

000

WDCNT

Monitors the count value of the 8-bit

up counter

The count value of the 8-bit up counter is read.

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