TMP89FS60 datasheet(87/410 Pages) TOSHIBA

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Page 73

TMP89FS60

RA000

5. Watchdog Timer (WDT)

The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu-

rious noises or the deadlock conditions, and return the CPU to a system recovery routine.

The watchdog timer signals used for detecting malfunctions can be programmed as watchdog interrupt request sig-

nals or watchdog timer reset signals.

Note: Care must be taken in system designing since the watchdog timer may not fulfill its functions due to disturbing noise

and other effects.

5.1

Configuration

Figure 5-1 Watchdog Timer Configuration

5.2

Control

The watchdog timer is controlled by the watchdog timer control register (WDCTR), the watchdog timer control

code register (WDCDR), the watchdog timer counter monitor (WDCNT) and the watchdog timer status (WDST).

The watchdog timer is enabled automatically just after the warm-up operation that follows reset is finished.

Watchdog timer control register

WDCTR

(0x0FD4)

76543

210

Bit Symbol

WDTEN

WDTW

WDTT

WDTOUT

Read/Write

R/W

After reset

10100

110

Source clock

Watchdog timer interrupt requestl

CPU/peripheral circuits reset

fcgck/2

or fs/2

fcgck/2

or fs/2

fcgck/2

or fs/2

fcgck/2

or fs/2

Watchdog timer reset signal

WDCTR

WDCDR

WDCNT

WDST

Overflow

Clear

Control code

decoder

Disable

control circuit

Disable code

(0xB1)

Clear code

(0x4E)

Clear time control circuit

8-bit up counter

Interrupt

request/reset

signal control

circuit

TMP89FS60 Datasheet(PDF) 87 Page - Toshiba Semiconductor

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