TMP89FS60 datasheet(48/410 Pages) TOSHIBA

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Page 34

2. CPU Core

2.3 System clock controller

TMP89FS60

RA001

Figure 2-11 IDLE0 and SLEEP0 Modes

• Start the IDLE0 and SLEEP0 modes

Stop (disable) the peripherals such as a timer counter.

To start the IDLE0 or SLEEP0 mode, set SYSCR2<TGHALT> to "1".

• Release the IDLE0 and SLEEP0 modes

The IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release

mode. These modes are selected at the interrupt master enable flag (IMF), the individual inter-

rupt enable flag (EF5) for the time base timer and TBTCR<TBTEN>. After releasing the

IDLE0 or SLEEP0 mode, SYSCR2<TGHALT> is automatically cleared to "0" and the opera-

tion mode is returned to the mode preceding the IDLE0 or SLEEP0 mode. If

TBTCR<TBTEN> has been set at "1", the INTTBT interrupt latch is set.

The IDLE0 and SLEEP0 modes are also released by a reset by the RESET pin, a power-on

reset and a reset by the voltage detection circuits. When a reset is released, the warm-up starts.

After the warm-up is completed, the NORMAL1 mode becomes active.

Reset

Yes

"0"

Yes

(Interrupt release mode)

(Normal release mode)

Yes

"1"

Stopping peripherals by

instructions

CPU and WDT stop

Interrupt processing

Reset input

TBT source clock

falling edge

TBTCR<TBTEN>

TBT interrupt

enabled

IMF = "1"

Starting IDLE0 or SLEEP0

mode by an instruction

Execution of the instruction

which follows the IDLE0 or

SLEEP0 mode start

instruction

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