ADS8699IPWR datasheet(25/74 Pages) TI2

25 / 74 page

beyond ±20 V, the internal node voltages surpass the break-down voltage for internal transistors, thus setting the

limit for overvoltage protection on the input pin.

The same overvoltage protection circuit also provides protection to the device when the device is not powered

on and AVDD is floating. This condition can arise when the input signals are applied before the ADC is fully

powered on. The overvoltage protection limits for this condition are shown in Table 7-2.

Table 7-2. Input Overvoltage Protection Limits When AVDD = Floating (1)

INPUT CONDITION

(VOVP = ±15 V)

TEST CONDITION

ADC OUTPUT

COMMENTS

CONDITION

RANGE

|VIN| < |VOVP|

Within overvoltage range

All input ranges

Invalid

Device is not functional but is protected internally by the

OVP circuit.

|VIN| > |VOVP|

Beyond overvoltage range

All input ranges

Invalid

This usage condition can cause irreversible damage to the

device.

(1)

AVDD = floating, GND = 0 V, AIN_GND = 0 V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the

break-down voltage for the internal OVP circuit. Assume that RS is approximately 0 Ω.

Figure 7-4 shows the I-V response of the internal overvoltage protection circuit when the device is not powered

on. According to this I-V response, the current flowing into the device input pin is limited by the 1-MΩ input

impedance. However, for voltages beyond ±15 V, the internal node voltage surpasses the break-down voltage

for internal transistors, thus setting the limit for overvoltage protection on the input pin.

Input voltage (V)

-30

-24

-18

-12

-6

-30

-20

-10

D005

Figure 7-3. I-V Curve for the Input OVP Circuit

(AVDD = 5 V)

Input voltage (V)

-20

-16

-12

-8

-4

-24

-18

-12

-6

D006

Figure 7-4. I-V Curve for the Input OVP Circuit

(AVDD = Floating)

7.3.4 Programmable Gain Amplifier (PGA)

The device features a programmable gain amplifier (PGA) as part of the analog signal-conditioning circuit that

converts the original single-ended input signal into a fully-differential signal to drive the internal SAR ADC. The

PGA also adjusts the common-mode level of the input signal before feeding it into the SAR ADC to ensure

maximum usage of the ADC input dynamic range. Depending on the range of the input signal, the PGA gain can

be adjusted by setting the RANGE_SEL[3:0] bits in the configuration register (see the RANGE_SEL_REG

range of ±3 × VREF. Table 7-3 lists the various configurations of the RANGE_SEL[3:0] bits for the different analog

input voltage ranges.

The PGA uses a precisely-matched network of resistors for multiple gain configurations. Matching between

these resistors is accurately trimmed to keep the overall gain error low across all input ranges.

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ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

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ADS8699IPWR Datasheet(PDF) 25 Page - Texas Instruments

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