ADS8699IPWR datasheet(61/74 Pages) TI2

61 / 74 page

9 Power Supply Recommendations

The device uses two separate power supplies: AVDD and DVDD. The internal circuits of the device operate on

AVDD and DVDD is used for the digital interface. AVDD and DVDD can be independently set to any value within

the permissible range.

9.1 Power Supply Decoupling

The AVDD supply pins must be decoupled with AGND by using a minimum 10-µF and 1-µF capacitor on each

supply. Place the 1-µF capacitor as close to the supply pins as possible. Place a minimum 10-µF decoupling

capacitor very close to the DVDD supply to provide the high-frequency digital switching current. The effect of

using the decoupling capacitor is illustrated in the difference between the power-supply rejection ratio (PSRR)

performance of the device. Figure 9-1 shows the PSRR of the device without using a decoupling capacitor. The

PSRR improves when the decoupling capacitors are used, as shown in Figure 9-2.

Input Frequency (Hz)

-80

-70

-60

-50

-40

-30

100

10k

100k

D057

± 12.288 V

± 10.24 V

± 6.144 V

± 5.12 V

± 2.56 V

0-12.288 V

0-10.24 V

0-6.144 V

0-5.12 V

Figure 9-1. PSRR Without a Decoupling Capacitor

Input Frequency (Hz)

-100

-90

-80

-70

-60

-50

100

10k

100k

D056

± 12.288 V

± 10.24 V

± 6.144 V

± 5.12 V

± 2.56 V

0-12.288 V

0-10.24 V

0-6.144 V

0-5.12 V

Figure 9-2. PSRR With a Decoupling Capacitor

9.2 Power Saving

In normal mode of operation, the device does not power down between conversions, and therefore achieves

high throughput.However, the device offers two programmable low-power modes: NAP and power-down (PD) to

reduce power consumption when the device is operated at lower throughput rates.

9.2.1 NAP Mode

In NAP mode, the internal blocks of the device are placed into a low-power mode to reduce the overall power

consumption of the device in the ACQ state.

To enable NAP mode:

• Write 69h to register address 05h to unlock the RST_PWRCTL_REG register.

• The NAP_EN bit in the RST_PWRCTL_REG register must be set to 1b. The CONVST/CS pin must be kept

high at the end of the conversion process. The device then enters NAP mode at the end of conversion and

remains in NAP mode as long as the CONVST/CS pin is held high.

A falling edge on the CONVST/CS brings the device out of NAP mode; however, the host controller can initiate a

new conversion (CONVST/CS rising edge) only after the tNAP_WKUP time has elapsed (see the Timing

Requirements: Asynchronous Reset table).

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ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

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ADS8699IPWR Datasheet(PDF) 61 Page - Texas Instruments

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