ADS8699IPWR datasheet(45/74 Pages) TI2

45 / 74 page

7.5.4.2 Protocols for Reading From the Device

The protocols for the data read operation can be broadly classified into three categories:

1. Legacy, SPI-compatible protocols with a single SDO-x

2. Legacy, SPI-compatible protocols with dual SDO-x

3. ADC master clock or source-synchronous (SRC) protocol for data transfer

7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x

As shown in Table 7-9, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S,

SPI-01-S, SPI-10-S, or SPI-11-S) to read data from the device.

Table 7-9. SPI Protocols for Reading From the Device

PROTOCOL

SCLK POLARITY

(At CS Falling

Edge)

SCLK PHASE

(Capture Edge)

MSB BIT

LAUNCH EDGE

SDI_CTL_REG

SDO_CTL_REG

DIAGRAM

SPI-00-S

Low

Rising

CS falling

00h

Figure 7-28

SPI-01-S

Low

Falling

1st SCLK rising

01h

00h

Figure 7-28

SPI-10-S

High

Falling

CS falling

02h

00h

Figure 7-29

SPI-11-S

High

Rising

1st SCLK falling

03h

00h

Figure 7-29

On power-up or after coming out of any asynchronous reset, the device supports the SPI-00-S protocol for data

read and data write operations. To select a different SPI-compatible protocol for both the data transfer

operations:

1. Program the SDI_MODE[1:0] bits in the SDI_CTL_REG register. This first write operation must adhere to the

SPI-00-S protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol.

2. Set the SDO_MODE[1:0] bits = 00b in the SDO_CTL_REG register.

Note

The SPI transfer protocol selected by configuring the SDI_MODE[1:0] bits in the SDI_CTL_REG

read from the device using the selected SPI protocol by configuring the SDO_MODE[1:0] bits = 00b in

the SDO_CTL_REG register, or one of the SRC protocols can be selected for data read, as explained

in the Source-Synchronous (SRC) Protocols section.

When using any of the SPI-compatible protocols, the RVS output remains low throughout the data transfer

frame; see the Timing Requirements: SPI-Compatible Serial Interface table for associated timing parameters.

Figure 7-28 and Figure 7-29 explain the details of the four protocols. As explained in the Data Transfer Frame

section, the host controller can use a short data transfer frame to read only the required number of MSB bits

from the 32-bit output data word.

If the host controller uses a long data transfer frame with SDO_CNTL_REG[7:0] = 00h, then the device exhibits

daisy-chain operation (see the Multiple Devices: Daisy-Chain Topology section).

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ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

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