ADS8699IPWR datasheet(46/74 Pages) TI2

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SCLK

SDO-0

M-1

M-2

L+1

RVS

CPOL = 0

CPOL = 1

CONVST/CS

Figure 7-28. Standard SPI Timing Protocol

(CPHA = 0, Single SDO-x)

SCLK

SDO-0

M-1

L+1

RVS

CPOL = 0

CPOL = 1

CONVST/CS

Figure 7-29. Standard SPI Timing Protocol

(CPHA = 1, Single SDO-x)

7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x

The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits

(dual SDO-x) when operating with any of the data transfer protocols. In order to operate the device in dual SDO

mode, the SDO1_CONFIG[1:0] bits in the SDO_CTL_REG register must be set to 11b. In this mode, the

ALARM/SDO-1/GPO pin functions as SDO-1.

In dual SDO mode, two bits of data are launched on the two SDO-x pins (SDO-0 and SDO-1) on every SCLK

launch edge, as shown in Figure 7-30 and Figure 7-31.

SCLK

SDO-1

M-2

M-4

L+3

L+1

RVS

CPOL = 0

CPOL = 1

CONVST/CS

SDO-0

M-1

M-3

M-5

L+2

Figure 7-30. Standard SPI Timing Protocol

(CPHA = 0, Dual SDO-x)

SCLK

SDO-1

M-2

L+3

L+1

RVS

CPOL = 0

CPOL = 1

CONVST/CS

M-1

L+2

SDO-0

Figure 7-31. Standard SPI Timing Protocol

(CPHA = 1, Dual SDO-x)

Note

For any particular SPI protocol, the device follows the same timing specifications for single and dual

SDO modes. The only difference is that the device requires half as many SCLK cycles to output the

same number of bits when in single SDO mode, thus reducing the minimum required SCLK frequency

for a certain sampling rate of the ADC.

ADS8691, ADS8695, ADS8699

SBAS777B – DECEMBER 2016 – REVISED MARCH 2021

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ADS8699IPWR Datasheet(PDF) 46 Page - Texas Instruments

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